PB

Per M. Bjesse

SY Synopsys: 11 patents #81 of 2,302Top 4%
SY Synopsis: 1 patents #1 of 39Top 3%
Overall (All Time): #413,456 of 4,157,543Top 10%
12
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
10657307 Using runtime information from solvers to measure quality of formal verification Himanshu Jain, Pratik Mahajan 2020-05-19
10592624 Efficient mechanism of fault qualification using formal verification Sandeep Jana, Arunava Saha, Pratik Mahajan, Alfred Koelbl 2020-03-17
10515170 Deep insight for debug using internal equivalence visualization and counter-example for sequential equivalence checking Sudipta Kundu 2019-12-24
10503853 Formal verification using cached search path information to verify previously proved/disproved properties Arunava Saha, Himanshu Jain, Manish Pandey, Ashvin M. Dsouza 2019-12-10
10325054 Invariant sharing to speed up formal verification Himanshu Jain, Carl Preston Pixley 2019-06-18
10089427 Method and apparatus for word-level netlist preprocessing and analysis using same 2018-10-02
9489477 Method and apparatus for word-level netlist reduction and verification using same 2016-11-08
8627260 Bit-level simplification of word-level models 2014-01-07
8104000 Method and apparatus for memory abstraction and for word level net list reduction and verification using same 2012-01-24
8001498 Method and apparatus for memory abstraction and verification using same 2011-08-16
7890894 Phase abstraction for formal verification James H. Kukula 2011-02-15
7343575 Phase abstraction for formal verification James H. Kukula 2008-03-11