Issued Patents All Time
Showing 1–25 of 60 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6597054 | Reduced pitch laser redundancy fuse bank structure | Kirk D. Prall, Tod S. Stone | 2003-07-22 |
| 6529426 | Circuit and method for varying a period of an internal control signal during a test mode | Todd A. Merritt | 2003-03-04 |
| 6208568 | Circuit for cancelling and replacing redundant elements | Adrian E. Ong | 2001-03-27 |
| 6201740 | Cache memories using DRAM cells with high-speed data path | Mirmajid Seyyedy | 2001-03-13 |
| RE36952 | One time programmable fully-testable programmable logic device with zero power and anti-fuse cell architecture | Kurt P. Douglas | 2000-11-14 |
| 6104645 | High speed global row redundancy system | Adrian E. Ong | 2000-08-15 |
| RE36821 | Wordline driver circuit having a directly gated pull-down device | Stephen L. Casper, Adrian E. Ong | 2000-08-15 |
| 6097647 | Efficient method for obtaining usable parts from a partially good memory integrated circuit | Brent Keeth, Adrian E. Ong | 2000-08-01 |
| 6044433 | DRAM cache | Mirmajid Seyyedy | 2000-03-28 |
| 5999480 | Dynamic random-access memory having a hierarchical data path | Adrian E. Ong, Troy A. Manning, Brent Keeth, Ken Waller | 1999-12-07 |
| 5991214 | Circuit and method for varying a period of an internal control signal during a test mode | Todd A. Merritt | 1999-11-23 |
| 5970008 | Efficient method for obtaining usable parts from a partially good memory integrated circuit | Brent Keeth, Adrian E. Ong | 1999-10-19 |
| 5953739 | Synchronous DRAM cache using write signal to determine single or burst write | Mirmajid Seyyedy | 1999-09-14 |
| 5933372 | Data path for high speed high bandwidth DRAM | Mirmajid Seyyedy | 1999-08-03 |
| 5912579 | Circuit for cancelling and replacing redundant elements | Adrian E. Ong | 1999-06-15 |
| 5905295 | Reduced pitch laser redundancy fuse bank structure | Kirk D. Prall, Tod S. Stone | 1999-05-18 |
| 5901105 | Dynamic random access memory having decoding circuitry for partial memory blocks | Adrian E. Ong, Troy A. Manning, Brent Keeth, Ken Waller | 1999-05-04 |
| 5850368 | Burst EDO memory address counter | Adrian E. Ong, Brett Williams, Troy A. Manning | 1998-12-15 |
| 5844833 | DRAM with open digit lines and array edge reference sensing | Mirmajid Seyyedy | 1998-12-01 |
| 5838620 | Circuit for cancelling and replacing redundant elements | Adrian E. Ong | 1998-11-17 |
| 5831918 | Circuit and method for varying a period of an internal control signal during a test mode | Todd A. Merritt | 1998-11-03 |
| 5812488 | Synchronous burst extended data out dram | Troy A. Manning, Todd A. Merritt | 1998-09-22 |
| 5802010 | Burst EDO memory device | Brett Williams, Troy A. Manning | 1998-09-01 |
| 5801996 | Data path for high speed high bandwidth DRAM | Mirmajid Seyyedy | 1998-09-01 |
| 5774412 | Local word line phase driver | George B. Raad, Todd A. Merritt | 1998-06-30 |