Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11544214 | Monolithic vector processor configured to operate on variable length vectors using a vector length register | Mayan Moudgill, Gary J. Nacer, C. John Glossner, Arthur Joseph Hoane, Murugappan Senthilvelan +3 more | 2023-01-03 |
| 10908909 | Processor with mode support | Mayan Moudgill, Gary J. Nacer, C. John Glossner, Arthur Joseph Hoane, Murugappan Senthilvelan | 2021-02-02 |
| 10733140 | Vector processor configured to operate on variable length vectors using instructions that change element widths | Mayan Moudgill, Arthur Joseph Hoane | 2020-08-04 |
| 10719451 | Variable translation-lookaside buffer (TLB) indexing | Mayan Moudgill, A. Joseph Hoane, Lei Wang, Gary J. Nacer, Aaron G. Milbury +1 more | 2020-07-21 |
| 10514915 | Computer processor with address register file | Mayan Moudgill, Gary J. Nacer, C. John Glossner, A. Joseph Hoane, Murugappan Senthilvelan +1 more | 2019-12-24 |
| 10339095 | Vector processor configured to operate on variable length vectors using digital signal processing instructions | Mayan Moudgill, Gary J. Nacer, C. John Glossner, Arthur Joseph Hoane, Murugappan Senthilvelan +3 more | 2019-07-02 |
| 10339094 | Vector processor configured to operate on variable length vectors with asymmetric multi-threading | Mayan Moudgill, Gary J. Nacer, C. John Glossner, Arthur Joseph Hoane, Murugappan Senthilvelan +3 more | 2019-07-02 |
| 10169039 | Computer processor that implements pre-translation of virtual addresses | Mayan Moudgill, Gary J. Nacer, C. John Glossner, A. Joseph Hoane, Murugappan Senthilvelan +1 more | 2019-01-01 |
| 9959246 | Vector processor configured to operate on variable length vectors using implicitly typed instructions | Mayan Moudgill, C. John Glossner, Arthur Joseph Hoane, Vitaly Kalashnikov | 2018-05-01 |
| 9940129 | Computer processor with register direct branches and employing an instruction preload structure | Mayan Moudgill, Gary J. Nacer, C. John Glossner, A. Joseph Hoane, Murugappan Senthilvelan +1 more | 2018-04-10 |
| 9910824 | Vector processor configured to operate on variable length vectors using instructions to combine and split vectors | Mayan Moudgill, Gary J. Nacer, C. John Glossner, Arthur Joseph Hoane, Murugappan Senthilvelan +1 more | 2018-03-06 |
| 9792116 | Computer processor that implements pre-translation of virtual addresses with target registers | Mayan Moudgill, Gary J. Nacer, C. John Glossner, A. Joseph Hoane, Murugappan Senthilvelan +1 more | 2017-10-17 |