Issued Patents All Time
Showing 1–25 of 93 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12419200 | Memory cell formation in three dimensional memory arrays using atomic layer deposition | Stephen W. Russell, Enrico Varesi, Lorenzo Fratin | 2025-09-16 |
| 12412626 | Accessing memory cells in a vertical memory array | Corrado Villa, Stefan Frederik Schippers, Lorenzo Fratin | 2025-09-09 |
| 12408332 | Memory devices having one-time-programmable fuses and/or antifuses formed from thin-film transistors | Lorenzo Fratin, Fabio Pellizzer | 2025-09-02 |
| 12396180 | Pillar and word line plate architecture for a memory array | Lorenzo Fratin, Enrico Varesi, Thomas M. Graettinger | 2025-08-19 |
| 12354707 | Word line structures for three-dimensional memory arrays | Stephen W. Russell, Lorenzo Fratin, Enrico Varesi | 2025-07-08 |
| 12302766 | Sparse piers for three-dimensional memory arrays | Stephen W. Russell, Enrico Varesi, David H. Wells, Lorenzo Fratin | 2025-05-13 |
| 12245438 | Dense piers for three-dimensional memory arrays | Stephen W. Russell, Enrico Varesi, David H. Wells, Lorenzo Fratin | 2025-03-04 |
| 12236999 | Decoder architectures for three-dimensional memory devices | Lorenzo Fratin, Fabio Pellizzer | 2025-02-25 |
| 12232432 | Memory cells with sidewall and bulk regions in vertical structures | Lorenzo Fratin, Enrico Varesi | 2025-02-18 |
| 12219784 | Memory device and method for manufacturing the same | Lorenzo Fratin, Fabio Pellizzer | 2025-02-04 |
| 12178054 | Split pillar architectures for memory devices | Fabio Pellizzer, Lorenzo Fratin | 2024-12-24 |
| 12171105 | Memory device with a split pillar architecture | Lorenzo Fratin, Fabio Pellizzer | 2024-12-17 |
| 12156411 | Memory array having air gaps | Paolo Tessariol, Enrico Varesi, Lorenzo Fratin | 2024-11-26 |
| 12150317 | Memory device and method for manufacturing the same | Lorenzo Fratin, Fabio Pellizzer | 2024-11-19 |
| 12148467 | Decoding for a memory device | Lorenzo Fratin, Fabio Pellizzer | 2024-11-19 |
| 12125555 | Matrix formation for performing computational operations in memory | Maurizio Rizzi | 2024-10-22 |
| 12068192 | Architecture of three-dimensional memory device and methods regarding the same | Lorenzo Fratin, Enrico Varesi | 2024-08-20 |
| 12045712 | Self select memory cell based artificial synapse | — | 2024-07-23 |
| 12002510 | Program current controller and sense circuit for cross-point memory devices | Andrea Ghetti, Andrea Martinelli, Efrem Bolandrina, Ferdinando Bedeschi | 2024-06-04 |
| 11997937 | Chalcogenide memory device compositions | Dale W. Collins, Lorenzo Fratin, Enrico Varesi | 2024-05-28 |
| 11957068 | Memory cells with sidewall and bulk regions in vertical structures | Lorenzo Fratin, Enrico Varesi | 2024-04-09 |
| 11948638 | Techniques for parallel memory cell access | Andrea Martinelli, Maurizio Rizzi | 2024-04-02 |
| 11943938 | Method for manufacturing a memory device and memory device manufactured through the same method | Lorenzo Fratin, Paolo Tessariol | 2024-03-26 |
| 11925036 | Three-dimensional memory array | Lorenzo Fratin | 2024-03-05 |
| 11903333 | Sidewall structures for memory cells in vertical structures | Lorenzo Fratin, Enrico Varesi | 2024-02-13 |