Issued Patents All Time
Showing 26–44 of 44 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6832307 | Instruction fetch buffer stack fold decoder for generating foldable instruction status information | — | 2004-12-14 |
| 6519682 | Pipelined non-blocking level two cache system with inherent transaction collision-avoidance | Charles A. Stack | 2003-02-11 |
| 6507928 | Processor cache system with parity protection and method of operation | — | 2003-01-14 |
| 6249851 | Computer system having non-blocking cache and pipelined bus interface unit | Charles A. Stack, Ut Nguyen | 2001-06-19 |
| 6208172 | System margin and core temperature monitoring of an integrated circuit | David R. Evoy | 2001-03-27 |
| 6205506 | Bus interface unit having multipurpose transaction buffer | — | 2001-03-20 |
| 6101568 | Bus interface unit having dual purpose transaction buffer | — | 2000-08-08 |
| 6021473 | Method and apparatus for maintaining coherency for data transaction of CPU and bus device utilizing selective flushing mechanism | Barry Davis, Brian Fall | 2000-02-01 |
| 5903773 | System to improve trapping of I/O instructions in a peripheral component interconnect bus computer system and method therefor | Barry Davis, Gary D. Hicok | 1999-05-11 |
| 5892978 | Combined consective byte update buffer | Gabriel R. Munguia, Ned D. Garinger | 1999-04-06 |
| 5842012 | Efficient soft reset in a personal computer | Gary Walker, David K. Cassetti | 1998-11-24 |
| 5764933 | Deadlock prevention in a two bridge system by flushing write buffers in the first bridge | David R. Evoy, Franklyn H. Story | 1998-06-09 |
| 5761454 | Deadlock resolution methods and apparatus for interfacing concurrent and asynchronous buses | Swaroop Adusumilli, Barry Davis, Brian Fall, Philip Wszolek | 1998-06-02 |
| 5619661 | Dynamic arbitration system and method | Michael R. Crews | 1997-04-08 |
| 5557781 | Combination asynchronous cache system and automatic clock tuning device and method therefor | Mitchell A. Stones | 1996-09-17 |
| 5483644 | Method for increasing cacheable address space in a second level cache | — | 1996-01-09 |
| 5454107 | Cache memory support in an integrated memory system | Judson A. Lehman, Mike Nakahara | 1995-09-26 |
| 5029070 | Coherent cache structures and methods | Daniel M. McCarthy, Joseph C. Circello, Gabriel R. Munguia | 1991-07-02 |
| 4928225 | Coherent cache structures and methods | Daniel M. McCarthy, Joseph C. Circello, Gabriel R. Munguia | 1990-05-22 |