| 12307182 |
Voltage impacts on delays for timing simulation |
Joao Geada |
2025-05-20 |
| 11934760 |
Voltage impacts on delays for timing simulation |
Joao Geada |
2024-03-19 |
| 11354475 |
Systems and methods for accurate voltage impact on integrated timing simulation |
Joao Geada, Ankur Gupta |
2022-06-07 |
| 7793243 |
Multi-engine static analysis |
Murat Becer, Joao Geada, Lee La France, Qian Shen |
2010-09-07 |
| 6877142 |
Timing verifier for MOS devices and related method |
Nevine Nassif, Madhav Desai, James Arthur Farrell, Harry Ray Fair, III, Roy Badeau |
2005-04-05 |
| 6654713 |
Method to compress a piecewise linear waveform so compression error occurs on only one side of the waveform |
Nevine Nassif, William J. Grundmann |
2003-11-25 |
| 6473888 |
Timing verifier for MOS devices and related method |
Nevine Nassif, Madhav Desai, James Arthur Farrell, Harry Ray Fair, III, Roy Badeau |
2002-10-29 |
| 6327686 |
Method for analyzing manufacturing test pattern coverage of critical delay circuit paths |
William J. Grundmann |
2001-12-04 |
| 6046984 |
Pruning of short paths in static timing verifier |
Joel Grodstein, Nevine Nassif |
2000-04-04 |
| 5657239 |
Timing verification using synchronizers and timing constraints |
Joel Grodstein, Jeng-Wei Pan |
1997-08-12 |
| 5648909 |
Static timing verification in the presence of logically false paths |
Larry L. Biro, Joel Grodstein, Jeng-Wei Pan |
1997-07-15 |