Issued Patents All Time
Showing 25 most recent of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12293137 | Processor core simulator including trace-based coherent cache driven memory traffic generator | — | 2025-05-06 |
| 11989136 | Methods and systems for translating virtual addresses in a virtual memory based system | Brian W. Thompto | 2024-05-21 |
| 11960893 | Multi-table instruction prefetch unit for microprocessor | Naga P. Gorti | 2024-04-16 |
| 11947461 | Prefetch unit filter for microprocessor | Naga P. Gorti, Guy L. Guthrie, Sanjeev Ghai | 2024-04-02 |
| 11886342 | Augmenting cache replacement operations | Aaron Dingler, Alper Buyuktosunoglu | 2024-01-30 |
| 11822922 | Miss-driven instruction prefetching | Naga P. Gorti | 2023-11-21 |
| 11816034 | Fast cache tracking to support aggressive prefetching | Naga P. Gorti | 2023-11-14 |
| 11645208 | Translation bandwidth optimized prefetching strategy through multiple translation lookaside buffers | David Campbell, Bryan Lloyd, George W. Rohrbaugh, III, Vivek Britto | 2023-05-09 |
| 11636045 | Translating virtual addresses in a virtual memory based system | Brian W. Thompto | 2023-04-25 |
| 11586440 | Link stack based instruction prefetch augmentation | Naga P. Gorti | 2023-02-21 |
| 11561796 | Linked miss-to-miss instruction prefetcher | Naga P. Gorti | 2023-01-24 |
| 11520585 | Prefetch store preallocation in an effective address-based cache directory | Bryan Lloyd, Brian W. Thompto, George W. Rohrbaugh, III, Vivek Britto | 2022-12-06 |
| 11520588 | Prefetch filter table for storing moderately-confident entries evicted from a history table | Edmund J. Gieske | 2022-12-06 |
| 11481219 | Store prefetches for dependent loads in a processor | Edmund J. Gieske, George W. Rohrbaugh, III | 2022-10-25 |
| 11461237 | Methods and systems for translating virtual addresses in a virtual memory based system | Brian W. Thompto | 2022-10-04 |
| 11301386 | Dynamically adjusting prefetch depth | Vivek Britto, George W. Rohrbaugh, III | 2022-04-12 |
| 11226817 | Prefetching workloads with dependent pointers | Donald R. Stence, John B. Griswell, Jr., Brian W. Thompto | 2022-01-18 |
| 11194575 | Instruction address based data prediction and prefetching | Naga P. Gorti, Edmund J. Gieske | 2021-12-07 |
| 11182161 | Fractional or partial line usage prediction in a processor | Edmund J. Gieske, Naga P. Gorti | 2021-11-23 |
| 11163695 | Methods and systems for translating virtual addresses in a virtual memory based system | Brian W. Thompto | 2021-11-02 |
| 11163683 | Dynamically adjusting prefetch depth | Edmund J. Gieske, Vivek Britto, George W. Rohrbaugh, III | 2021-11-02 |
| 11151054 | Speculative address translation requests pertaining to instruction cache misses | Naga P. Gorti | 2021-10-19 |
| 11093248 | Prefetch queue allocation protection bubble in a processor | Vivek Britto, George W. Rohrbaugh, III, Brian W. Thompto | 2021-08-17 |
| 11016900 | Limiting table-of-contents prefetching consequent to symbol table requests | Edmund J. Gieske | 2021-05-25 |
| 10963249 | Processor prefetcher mode governor for switching between prefetch modes | Vivek Britto, George W. Rohrbaugh, III, Brian W. Thompto | 2021-03-30 |