| 12393754 |
Generating a reduced block model view on-the-fly |
Soumen Ghosh, Mark Roizman, Vijaya V. Varkey, Abhinav Singla, Rajarshi Mukherjee |
2025-08-19 |
| 9990453 |
Clock-domain-crossing specific design mutations to model silicon behavior and measure verification robustness |
Namit Gupta, Jean-Marc A. Forey, Horia Alexandru Toma |
2018-06-05 |
| 9886753 |
Verification of circuit structures including sub-structure variants |
Namit Gupta, Kaushik De, Rajarshi Mukherjee, Suman Nandan, Subhamoy Pal |
2018-02-06 |
| 9792394 |
Accurate glitch detection |
Kaushik De, Dipti Ranjan Senapati, Namit Gupta, Rajarshi Mukherjee |
2017-10-17 |
| 9529948 |
Minimizing crossover paths for functional verification of a circuit description |
Kaushik De, Rajarshi Mukherjee, Namit Gupta |
2016-12-27 |
| 9032339 |
Ranking verification results for root cause analysis |
Kaushik De, Kevin M. Harer, Rajarshi Mukherjee |
2015-05-12 |