LS

Louis K. Scheffer

CS Cadence Design Systems: 33 patents #11 of 2,263Top 1%
SY Synopsys: 2 patents #669 of 2,302Top 30%
Overall (All Time): #99,104 of 4,157,543Top 3%
35
Patents All Time

Issued Patents All Time

Showing 26–35 of 35 patents

Patent #TitleCo-InventorsDate
7254798 Method and apparatus for designing integrated circuit layouts Steven Teig 2007-08-07
7249342 Method and system for context-specific mask writing Robert C. Pack 2007-07-24
7231628 Method and system for context-specific mask inspection Robert C. Pack 2007-06-12
7207024 Automatic insertion of clocked elements into an electronic design to improve system performance 2007-04-17
7082588 Method and apparatus for designing integrated circuit layouts Steven Teig 2006-07-25
7024638 Method for creating patterns for producing integrated circuits Kenji Yoshida, Yoshikuni Abe, Aki Fujimura, Robert C. Pack 2006-04-04
6543041 Method and apparatus for reducing signal integrity and reliability problems in ICS through netlist changes during placement Jeffrey S. Salowe 2003-04-01
6529913 Database for electronic design automation applications Robert Cameron Doig 2003-03-04
5625580 Hardware modeling system and method of use Andrew Read, Mark S. Papamarcos, Wayne Phillip Heideman, Robert Kristianto Mardjuki, Robert K. Couch +3 more 1997-04-29
5353243 Hardware modeling system and method of use Andrew Read, Mark S. Papamarcos, Wayne Phillip Heideman, Robert Kristianto Mardjuki, Robert K. Couch +3 more 1994-10-04