Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10712800 | Aligning active and idle phases in a mixed workload computing platform | Benjamin Tsien, Alexander J. Branover, Ming L. So, Philip Ng, Xiao Gang Zheng +4 more | 2020-07-14 |
| 5740402 | Conflict resolution in interleaved memory systems with multiple parallel accesses | Joseph P. Bratt, John F. Brennen, Peter Hsu, Man Kit Tang, Steven J. Ciavaglia | 1998-04-14 |
| 5632025 | Method for preventing multi-level cache system deadlock in a multi-processor system | Joseph P. Bratt, John Brennan, Peter Hsu, William A. Huffman, Steve J. Ciavaglia | 1997-05-20 |
| 5572704 | System and method for controlling split-level caches in a multi-processor system including data loss and deadlock prevention schemes | Joseph P. Bratt, John Brennan, Peter Hsu, William A. Huffman, Steve Ciavagia | 1996-11-05 |
| 5537538 | Debug mode for a superscalar RISC processor | Joseph P. Bratt, John Brennan, Peter Hsu, Chandra Joshi, William A. Huffman +3 more | 1996-07-16 |
| 5526504 | Variable page size translation lookaside buffer | Peter Hsu, Steve J. Ciavaglia | 1996-06-11 |
| 5510934 | Memory system including local and global caches for storing floating point and integer data | John Brennan, Peter Hsu, William A. Huffman, Paul Rodman, Man Kit Tang +1 more | 1996-04-23 |