| 5349651 |
System for translation of virtual to physical addresses by operating memory management processor for calculating location of physical address in memory concurrently with cache comparing virtual addresses for translation |
Ricky C. Hetherington, David A. Webb, David B. Fite, Jr., Tryggve Fossum, Dwight P. Manley |
1994-09-20 |
| 5222223 |
Method and apparatus for ordering and queueing multiple memory requests |
David A. Webb, Ricky C. Hetherington, Tryggve Fossum, Dwight P. Manley |
1993-06-22 |
| 5167026 |
Simultaneously or sequentially decoding multiple specifiers of a variable length pipeline instruction based on detection of modified value of specifier registers |
David B. Fite, Jr., Mark A. Firstenberg, Lawrence O. Herman, Ronald M. Salett |
1992-11-24 |
| 5148528 |
Method and apparatus for simultaneously decoding three operands in a variable length instruction when one of the operands is also of variable length |
David B. Fite, Jr., Tryggve Fossum |
1992-09-15 |
| 5142634 |
Branch prediction |
David B. Fite, Jr., Dwight P. Manley, Michael M. McKeon, Elaine H. Fite, Ronald M. Salett +1 more |
1992-08-25 |
| 5142631 |
System for queuing individual read or write mask and generating respective composite mask for controlling access to general purpose register |
Mark A. Firstenberg, David B. Fite, Jr., Michael M. McKeon, Wiliam R. Grundmann, David A. Webb +4 more |
1992-08-25 |
| 5142633 |
Preprocessing implied specifiers in a pipelined processor |
David B. Fite, Jr., Mark A. Firstenberg |
1992-08-25 |
| 5125083 |
Method and apparatus for resolving a variable number of potential memory access conflicts in a pipelined computer system |
David B. Fite, Jr., Tryggve Fossum, Ricky C. Hetherington, Jr. David A. Webb |
1992-06-23 |
| 5113515 |
Virtual instruction cache system using length responsive decoded instruction shifting and merging with prefetch buffer outputs to fill instruction buffer |
David B. Fite, Jr., Ricky C. Hetherington, Michael M. McKeon, Dwight P. Manley |
1992-05-12 |
| 5109495 |
Method and apparatus using a source operand list and a source operand pointer queue between the execution unit and the instruction decoding and operand processing units of a pipelined data processor |
David B. Fite, Jr., Tryggve Fossum, William R. Grundmann, Dwight P. Manely, Francis X. McKeen +3 more |
1992-04-28 |
| 4985825 |
System for delaying processing of memory access exceptions until the execution stage of an instruction pipeline of a virtual memory system based digital computer |
David A. Webb, David B. Fite, Jr., Ricky C. Hetherington, Francis X. McKeen, Mark A. Firstenberg +3 more |
1991-01-15 |
| 4982402 |
Method and apparatus for detecting and correcting errors in a pipelined computer system |
Richard C. Beaven, Michael B. Evans, Tryggve Fossum, Ricky C. Hetherington, William R. Grundmann +1 more |
1991-01-01 |
| 4888679 |
Method and apparatus using a cache and main memory for both vector processing and scalar processing by prefetching cache blocks including vector data elements |
Tryggve Fossum, Ricky C. Hetherington, David B. Fite, Jr., Dwight P. Manley, Francis X. McKeen |
1989-12-19 |
| 4548002 |
Roof for a mobile home or the like |
— |
1985-10-22 |
| 4380797 |
Two level store with many-to-one mapping scheme |
Peter L. L. Desyllas, Barry Gordon Radley, Alasdair Rawsthorne, John R. Eaton |
1983-04-19 |