Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12006111 | Packaging comprising a container and a cap with hinged lid | Kelly Greenberg, Richard Jentis, Tran Nguyen | 2024-06-11 |
| 9274709 | Indicators for storage cells | Richard J. Tomaszewski, Michael S. Bunker | 2016-03-01 |
| 8627109 | Method of securing access to a hard disk drive of a computer system with an enhanced security mode | — | 2014-01-07 |
| 8495757 | System and method for placing an electronic apparatus into a protected state in response to environmental data | Leonard E. Russo, Walter A. Gaspard, Richard J. Tomaszewski, Robert C. Elliott | 2013-07-23 |
| 6272580 | Apparatus and method for dynamically elevating a lower level bus master to an upper level bus master within a multi-level arbitration system | Jeff Stevens, Robert A. Lester, Phillip M. Jones, Peter Bow Kwong Lee | 2001-08-07 |
| 6226700 | Computer system with bridge logic that includes an internal modular expansion bus and a common master interface for internal master devices | Shaun Wandler, Jeffrey C. Stevens, Robert L. Woods, Danny Higby, Russ Wunderlich +2 more | 2001-05-01 |
| 6101566 | Computer system with bridge logic that includes an internal modular expansion bus and a common target interface for internal target devices | Robert L. Woods, Jeffrey C. Stevens, Shaun Wandler, Todd Deschepper, Jeffrey Wilson +2 more | 2000-08-08 |
| 5884095 | Direct memory access controller having programmable timing | Robert A. Lester | 1999-03-16 |
| 5802318 | Universal serial bus keyboard system | David E. Murray, David R. Wooten, Jr., Randall L. Hess, Christopher C. Wanner | 1998-09-01 |
| 5748888 | Method and apparatus for providing secure and private keyboard communications in computer systems | Michael F. Angelo | 1998-05-05 |
| 5692216 | Direct memory access controller having programmable timing | Robert A. Lester | 1997-11-25 |
| 5603050 | Direct memory access controller having programmable timing | Robert A. Lester | 1997-02-11 |
| 5596729 | First arbiter coupled to a first bus receiving requests from devices coupled to a second bus and controlled by a second arbiter on said second bus | Robert A. Lester | 1997-01-21 |
| 5559968 | Non-conforming PCI bus master timing compensation circuit | Charles J. Stancil, William M. Vaughn | 1996-09-24 |
| 5553248 | System for awarding the highest priority to a microprocessor releasing a system bus after aborting a locked cycle upon detecting a locked retry signal | Maria L. Melo, Michael Moriarty, Paul R. Culley, Arnold Thomas Schnell | 1996-09-03 |
| 5463753 | Method and apparatus for reducing non-snoop window of a cache controller by delaying host bus grant signal to the cache controller | Walter G. Fry | 1995-10-31 |
| 5434997 | Method and apparatus for testing and debugging a tightly coupled mirrored processing system | John A. Landry, Walter G. Fry, Roger E. Tipley | 1995-07-18 |
| 5353415 | Method and apparatus for concurrency of bus operations | Walter G. Fry | 1994-10-04 |