Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9262571 | Layout migration with hierarchical scale and bias method | — | 2016-02-16 |
| 6577992 | Transistor level circuit simulator using hierarchical data | Andrei Tcherniaev, Iouri Feinberg, Walter Chan, An-Chang Deng | 2003-06-10 |
| 6311147 | Integrated circuit power net analysis | Peiqi He | 2001-10-30 |
| 6249898 | Method and system for reliability analysis of CMOS VLSI circuits based on stage partitioning and node activities | Han Young Koh, Tak K. Young | 2001-06-19 |
| 5933358 | Method and system of performing voltage drop analysis for power supply networks of VLSI circuits | Han Young Koh, Tak K. Young | 1999-08-03 |
| 5878053 | Hierarchial power network simulation and analysis tool for reliability testing of deep submicron IC designs | Han Young Koh, Tak K. Young, Chiping Ju, Hurley Song | 1999-03-02 |
| 5872952 | Integrated circuit power net analysis through simulation | Peiqi He | 1999-02-16 |