Issued Patents All Time
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8954905 | Methods for physical layout estimation | Denis Baylor, Matthew Robert Rardon | 2015-02-10 |
| 8560984 | Methods and systsm for physical layout estimation | Denis Baylor, Matthew Robert Rardon | 2013-10-15 |
| 8386978 | Software and systems for physical layout estimation | Denis Baylor, Matthew Robert Rardon | 2013-02-26 |
| 8127260 | Physical layout estimator | Denis Baylor, Matthew Robert Rardon | 2012-02-28 |
| 5878053 | Hierarchial power network simulation and analysis tool for reliability testing of deep submicron IC designs | Han Young Koh, Jeh-Fu Tuan, Tak K. Young, Chiping Ju | 1999-03-02 |