Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6249898 | Method and system for reliability analysis of CMOS VLSI circuits based on stage partitioning and node activities | Han Young Koh, Jeh-Fu Tuan | 2001-06-19 |
| 5933358 | Method and system of performing voltage drop analysis for power supply networks of VLSI circuits | Han Young Koh, Jeh-Fu Tuan | 1999-08-03 |
| 5878053 | Hierarchial power network simulation and analysis tool for reliability testing of deep submicron IC designs | Han Young Koh, Jeh-Fu Tuan, Chiping Ju, Hurley Song | 1999-03-02 |