Issued Patents All Time
Showing 25 most recent of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11647623 | Method for manufacturing semiconductor structure with buried power line and buried signal line | Chiang-Lin Shih, Tseng-Fu Lu | 2023-05-09 |
| 11342818 | Encoder, motor and controlling method of encoder | Ching-Hsiung Tsai, Chieh-Huang Lu, Hui-Chun Chu, Min-Ling Huang | 2022-05-24 |
| 11315928 | Semiconductor structure with buried power line and buried signal line and method for manufacturing the same | Chiang-Lin Shih, Tseng-Fu Lu | 2022-04-26 |
| 11002562 | Encoder using a magnetic sensing assembly and an optical sensing assembly and position detection method for a motor | Horng-Jou Wang | 2021-05-11 |
| 10761507 | Instant correction method for encoder and system thereof | Ching-Hsiung Tsai, Yu-Hua Chiao | 2020-09-01 |
| 10090154 | Method for preparing a semiconductor structure having second line patterns and third line patterns formed over first line patterns | Chiang-Lin Shih, Shing-Yih Shih | 2018-10-02 |
| 9779957 | Method of manufacturing independent depth-controlled shallow trench isolation | Shian-Jyh Lin, Chin-Piao Chang, Jen-Jui Huang | 2017-10-03 |
| 8395209 | Single-sided access device and fabrication method thereof | Hsin-Jung Ho, Neng-Tai Shih, Chang-Rong Wu, Chiang-Hung Lin, CHIH-HUANG WU | 2013-03-12 |
| 8343829 | Recessed-gate transistor device having a dielectric layer with multi thicknesses and method of making the same | Jer-Chyi Wang, Tieh-Chiang Wu, Chung-Yuan Lee | 2013-01-01 |
| 7994559 | Recessed-gate transistor device having a dielectric layer with multi thicknesses and method of making the same | Jer-Chyi Wang, Tieh-Chiang Wu, Chung-Yuan Lee | 2011-08-09 |
| 7759190 | Memory device and fabrication method thereof | Neng-Tai Shih | 2010-07-20 |
| 7678692 | Fabrication method for a damascene bit line contact plug | Yi-Nan Chen, Chih-Ching Lin, Hui-Min Mao | 2010-03-16 |
| 7622770 | Semiconductor device having a trench gate and method of fabricating the same | Pei-Ing Lee | 2009-11-24 |
| 7541244 | Semiconductor device having a trench gate and method of fabricating the same | Pei-Ing Lee | 2009-06-02 |
| 7285377 | Fabrication method for a damascene bit line contact plug | Yi-Nan Chen, Chih-Ching Lin, Hui-Min Mao | 2007-10-23 |
| 7144799 | Method for pre-retaining CB opening | Yinan Chen, Feng Lin | 2006-12-05 |
| 7109094 | Method for preventing leakage in shallow trench isolation | Ming-Cheng Chang, Yi-Nan Chen | 2006-09-19 |
| 7005698 | Split gate flash memory cell | Chi-Hui Lin, Pei-Ing Lee, Jih-Chang Lien | 2006-02-28 |
| 6958521 | Shallow trench isolation structure | Ming-Cheng Chang, Yi-Nan Chen | 2005-10-25 |
| 6919245 | Dynamic random access memory cell layout and fabrication method thereof | Ming-Cheng Chang, Tieh-Chiang Wu, Yi-Nan Chen | 2005-07-19 |
| 6909136 | Trench-capacitor DRAM cell having a folded gate conductor | Yinan Chen, Ming-Cheng Chang, Tse-Yao Huang, Change-Rong Wu, Hui-Min Mao | 2005-06-21 |
| 6801462 | Device and method for detecting alignment of deep trench capacitors and word lines in DRAM devices | Ming-Cheng Chang, Tie Jiang Wu | 2004-10-05 |
| 6800895 | Vertical split gate flash memory cell and method for fabricating the same | Ming-Cheng Chang, Cheng-Chih Huang | 2004-10-05 |
| 6794250 | Vertical split gate flash memory cell and method for fabricating the same | Ming-Cheng Chang, Cheng-Chih Huang | 2004-09-21 |
| 6788598 | Test key for detecting overlap between active area and deep trench capacitor of a DRAM and detection method thereof | Ming-Cheng Chang, Tie Jiang Wu, Tse-Main Kuo, Hsu-Cheng Fan | 2004-09-07 |