Issued Patents All Time
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10776277 | Partial memory die with inter-plane re-mapping | Daniel Linnen, Srikar Peesari, Kirubakaran Periyannan, Avinash Rajagiri, Shantanu Gupta +2 more | 2020-09-15 |
| 10564861 | Parity relocation for reducing temperature throttling | Daniel Linnen, Dongxiang Liao, Avinash Rajagiri, Ashish Ghai, Abhinav Anand | 2020-02-18 |
| 10290354 | Partial memory die | Daniel Linnen, Srikar Peesari, Kirubakaran Periyannan, Avinash Rajagiri, Shantanu Gupta +4 more | 2019-05-14 |
| 10242750 | High-speed data path testing techniques for non-volatile memory | Daniel Linnen, Srikar Peesari, Kirubakaran Periyannan, Shantanu Gupta, Avinash Rajagiri +2 more | 2019-03-26 |
| 10032524 | Techniques for determining local interconnect defects | Sagar Magia, Jayavel Pachamuthu | 2018-07-24 |
| 9953717 | NAND structure with tier select gate transistors | Jayavel Pachamuthu, Peter Rabkin | 2018-04-24 |
| 9934872 | Erase stress and delta erase loop count methods for various fail modes in non-volatile memory | Sagar Magia, Jayavel Pachamuthu | 2018-04-03 |
| 9881929 | Multi-tier memory stack structure containing non-overlapping support pillar structures and method of making thereof | Pradhyumna Ravikirthi, Jayavel Pachamuthu, Peter Rabkin | 2018-01-30 |
| 9830998 | Stress patterns to detect shorts in three dimensional non-volatile memory | Jayavel Pachamuthu, Sagar Magia, Ankitkumar Babariya | 2017-11-28 |
| 9653175 | Determination of word line to word line shorts between adjacent blocks | Sagar Magia, Khanh Nguyen | 2017-05-16 |
| 9564219 | Current based detection and recording of memory hole-interconnect spacing defects | Sagar Magia, Jayavel Pachamuthu, Ankitkumar Babariya | 2017-02-07 |
| 9548129 | Word line look ahead read for word line to word line short detection | Rajan Paudel, Mrinal Kochar, Sagar Magia | 2017-01-17 |
| 9530514 | Select gate defect detection | Jayavel Pachamuthu, Sagar Magia | 2016-12-27 |
| 9514835 | Determination of word line to word line shorts between adjacent blocks | Sagar Magia, Khanh Nguyen | 2016-12-06 |
| 9496040 | Adaptive multi-page programming methods and apparatus for non-volatile memory | Rajan Paudel, Sagar Magia | 2016-11-15 |
| 9484086 | Determination of word line to local source line shorts | Sagar Magia | 2016-11-01 |
| 9460809 | AC stress mode to screen out word line to word line shorts | Sagar Magia | 2016-10-04 |
| 9449698 | Block and zone erase algorithm for memory | Rajan Paudel, Sagar Magia | 2016-09-20 |
| 9449694 | Non-volatile memory with multi-word line select for defect detection operations | Rajan Paudel, Sagar Magia, Khanh Nguyen | 2016-09-20 |
| 9269446 | Methods to improve programming of slow cells | Sagar Magia, Jayavel Pachamuthu, Ankitkumar Babariya | 2016-02-23 |
| 9240249 | AC stress methods to screen out bit line defects | Sagar Magia, Jayavel Pachamuthu | 2016-01-19 |
| 9224502 | Techniques for detection and treating memory hole to local interconnect marginality defects | Sagar Magia, Jayavel Pachamuthu, Deepak Raghu | 2015-12-29 |
| 9202593 | Techniques for detecting broken word lines in non-volatile memories | Sagar Magia, Tien-Chien Kuo, Jayavel Pachamuthu | 2015-12-01 |