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Translation of virtual addresses to physical addresses using translation lookaside buffer information |
Piyush Patel, Rakesh ANIGUNDI, Sadayan Ghows Ghani Sadayan Ebramsah Mo Abdul |
2020-08-25 |
| 8539404 |
Functional simulation redundancy reduction by state comparison and pruning |
Jesse E. Craig |
2013-09-17 |
| 8347019 |
Structure for hardware assisted bus state transition circuit using content addressable memories |
Serafino Bueti, Kenneth J. Goodnow, Todd E. Leonard, Gregory J. Mann, Clarence R. Ogilvie +2 more |
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Critical path redundant logic for mitigation of hardware across chip variation |
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2011-03-01 |
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System and method for system-on-chip interconnect verification |
Serafino Bueti, Adam J. Courchesne, Kenneth J. Goodnow, Gregory J. Mann, Stanley B. Stanski +1 more |
2011-01-04 |
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Transition balancing for noise reduction/Di/Dt reduction during design, synthesis, and physical design |
Igor Arsovski, Serafino Bueti, Joseph A. Iadanza, Hemen R. Shah, Sebastian T. Ventrone |
2010-10-26 |
| 7743270 |
Assigning clock arrival time for noise reduction |
Igor Arsovski, Joseph A. Iadanza, Sebastian T. Ventrone |
2010-06-22 |
| 7643591 |
Transition balancing for noise reduction /Di/Dt reduction during design, synthesis, and physical design |
Igor Arsovski, Serafino Bueti, Joseph A. Iadanza, Hemen R. Shah, Sebastian T. Ventrone |
2010-01-05 |
| 7519941 |
Method of manufacturing integrated circuits using pre-made and pre-qualified exposure masks for selected blocks of circuitry |
Serafino Bueti, Kenneth J. Goodnow, Gregory J. Mann |
2009-04-14 |
| 7313738 |
System and method for system-on-chip interconnect verification |
Serafino Bueti, Adam J. Courchesne, Kenneth J. Goodnow, Gregory J. Mann, Stanley B. Stanski +1 more |
2007-12-25 |
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Circuit design verification using checkpointing |
Jesse E. Craig |
2007-12-11 |
| 7286770 |
Fiber optic transmission lines on an SOC |
Gary R. Doyle, Kenneth J. Goodnow, Riyon Harding, Francis A. Kampf, Sebastian T. Ventrone |
2007-10-23 |
| 7275011 |
Method and apparatus for monitoring integrated circuit temperature through deterministic path delays |
Serafino Bueti, Adam J. Courchesne, Kenneth J. Goodnow, Stanley B. Stanski, Scott T. Vento |
2007-09-25 |
| 7248838 |
Wireless communication system within a system on a chip |
Kenneth J. Goodnow, Riyon Harding, Charles J. Masenas, Sebastian T. Ventrone |
2007-07-24 |
| 7139881 |
Semiconductor device comprising a plurality of memory structures |
Kenneth J. Goodnow, Francis A. Kampf, Sebastian T. Ventrone |
2006-11-21 |
| 7103320 |
Wireless communication system within a system on a chip |
Kenneth J. Goodnow, Riyon Harding, Charles J. Masenas, Sebastian T. Ventrone |
2006-09-05 |
| 7091743 |
Data acknowledgment using impedance mismatching |
Michael J. Boudreaux, Adam J. Courchesne, Mark S. Styduhar, Sebastian T. Ventrone |
2006-08-15 |
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System and method for correcting timing signals in integrated circuits |
Kenneth J. Goodnow, Peter Joel Jenkins, Francis A. Kampf, Sebastian T. Ventrone |
2006-08-01 |
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Auto-linking of function logic state with testcase regression list |
Nancy H. Pratt, Sebastian T. Ventrone |
2005-08-23 |
