| 9891277 |
Secure low voltage testing |
Joel Ray Knight, Stefano Pietri, Steven K. Watkins |
2018-02-13 |
| 8717829 |
System and method for soft error detection in memory devices |
Ashish Sharma, Amit Gupta, Thomas W. Liston, Jehoda Refaeli |
2014-05-06 |
| 8386747 |
Processor and method for dynamic and selective alteration of address translation |
William C. Moyer |
2013-02-26 |
| 8380918 |
Non-volatile storage alteration tracking |
Richard Soja, Timothy J. Strauss |
2013-02-19 |
| 7809980 |
Error detector in a cache memory using configurable way redundancy |
Jehoda Refaeli, Florian Bogenberger |
2010-10-05 |
| 6499092 |
Method and apparatus for performing access censorship in a data processing system |
Wallace B. Harwood, III, Thomas R. Toms |
2002-12-24 |
| 6240493 |
Method and apparatus for performing access censorship in a data processing system |
Wallace B. Hardwood, III, Thomas R. Toms |
2001-05-29 |
| 6079015 |
Data processing system having selectable exception table relocation and method therefor |
Wallace B. Harwood, III, Rami Natan, Yossi Asher, Avi Ginsberg |
2000-06-20 |
| 6052746 |
Integrated circuit having programmable pull device configured to enable/disable first function in favor of second function according to predetermined scheme before/after reset |
Seshagiri Prasad Kalluri, Rene M. Delgado |
2000-04-18 |
| 5737566 |
Data processing system having a memory with both a high speed operating mode and a low power operating mode and method therefor |
Robert W. Sparks, Wallace B. Harwood, III, Thomas Jew |
1998-04-07 |
| 5727172 |
Method and apparatus for performing atomic accesses in a data processing system |
Adi Sapir, Wallace B. Harwood, III |
1998-03-10 |
| 5717931 |
Method and apparatus for communicating between master and slave electronic devices where the slave device may be hazardous |
Adi Sapir, Ilan Pardo, Wallace B. Harwood, III, John J. Vaglica, Danny Shterman |
1998-02-10 |
| 5699516 |
Method and apparatus for implementing a in-order termination bus protocol within a data processing system |
Adi Sapir |
1997-12-16 |
| 5675749 |
Method and apparatus for controlling show cycles in a data processing system |
Jay A. Hartvigsen, Wallace B. Harwood, III, Jeffrey A. Hopkins |
1997-10-07 |
| 5651138 |
Data processor with controlled burst memory accesses and method therefor |
Chinh H. Le, Wallace B. Harwood, III |
1997-07-22 |
| 5649159 |
Data processor with a multi-level protection mechanism, multi-level protection circuit, and method therefor |
Chinh H. Le |
1997-07-15 |
| 5617559 |
Modular chip select control circuit and method for performing pipelined memory accesses |
Chinh H. Le |
1997-04-01 |
| 5511182 |
Programmable pin configuration logic circuit for providing a chip select signal and related method |
Chinh H. Le, Basil J. Jackson |
1996-04-23 |
| 5448744 |
Integrated circuit microprocessor with programmable chip select logic |
John J. Vaglica, James C. Smallwood, Mark W. McDermott, Hiroyuki Sugiyama, William P. LaViolette +1 more |
1995-09-05 |
| 5329621 |
Microprocessor which optimizes bus utilization based upon bus speed |
Bradley Gene Burgess, Michael S. Taborn |
1994-07-12 |
| 5276824 |
Data processor having a multi-stage instruction pipe and selection logic responsive to an instruction decoder for selecting one stage of the instruction pipe |
Robert J. Skruhak, James C. Nash |
1994-01-04 |
| 5241637 |
Data processor microsequencer having multiple microaddress sources and next microaddress source selection |
Robert J. Skruhak, James C. Nash |
1993-08-31 |
| 5072365 |
Direct memory access controller using prioritized interrupts for varying bus mastership |
Bradley Gene Burgess, John P. Dunn |
1991-12-10 |
