Issued Patents All Time
Showing 1–25 of 60 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12332305 | Circuit and method to measure simulation to silicon timing correlation | Ashish Nayak, Anshul Varma, Anand Rajagopalan | 2025-06-17 |
| 12216159 | Circuit and method to measure simulation to silicon timing correlation | Ashish Nayak, Anshul Varma, Anand Rajagopalan | 2025-02-04 |
| 11835580 | Circuit and method to measure simulation to silicon timing correlation | Ashish Nayak, Anshul Varma, Anand Rajagopalan | 2023-12-05 |
| 11418203 | Frequency locked loops and related circuits and methods | Ashish Nayak | 2022-08-16 |
| 10732701 | Method and apparatus of dual threshold clock control | Lee-Kee Yong, Rolf Lagerquist | 2020-08-04 |
| 10361190 | Standard cell circuitries | Kin-Hooi Dia, Shao-Hua Huang, Wen-Yi Lin | 2019-07-23 |
| 10345882 | Dynamic power meter with improved accuracy and single cycle resolution | Huajun Wen, Hsin-Chen Chen, Brian Flachs | 2019-07-09 |
| 10275010 | Fast and Autonomous mechanism for CPU OC protection | Sumanth Katte Gururajarao, Gordon Gammie, Alice Wang, Uming Ko, Rolf Lagerquist | 2019-04-30 |
| 9690365 | Dual-rail power equalizer | Yi-Te Chiu, Che-Wei Wu, Lee-Kee Yong, Chia-Wei Wang, Cheng-Hsing Chien +1 more | 2017-06-27 |
| 9600024 | Control method of clock gating for dithering in the clock signal to mitigate voltage transients | Gordon Gammie, Alice Wang, Uming Ko | 2017-03-21 |
| 9224642 | Conductive via structures for routing porosity and low via resistance, and processes of making | — | 2015-12-29 |
| 8964880 | Reduction in power supply induced jitter on a SerDes transmitter | Vishnu Ravinuthula, Dushmantha Bandara Rajapaksha | 2015-02-24 |
| 8872344 | Conductive via structures for routing porosity and low via resistance, and processes of making | — | 2014-10-28 |
| 8812885 | Detecting wake-up events for a chip based on an I/O power supply | Philippe Royannez, Gilles Dubost, Christophe Vatinel, William Douglas Wilson, Vinod Menezes +1 more | 2014-08-19 |
| 8564351 | Clock phase compensation for adjusted voltage circuits | Jie Gu, Gordon Gammie | 2013-10-22 |
| 8437214 | Memory cell employing reduced voltage | Donald George Mikan, Jr., Theodore W. Houston, Michael Patrick Clinton | 2013-05-07 |
| 8378653 | HDMI driver tail current transistors with current mirror controlled leads | — | 2013-02-19 |
| 8300451 | Two word line SRAM cell with strong-side word line boost for write provided by weak-side word line | Theodore W. Houston | 2012-10-30 |
| 8301431 | Apparatus and method for accelerating simulations and designing integrated circuits and other systems | Keerthinarayan P. Heragu, Theodore W. Houston, Anand Seshadri | 2012-10-30 |
| 8278980 | Enhancement of power management using dynamic voltage and frequency scaling and digital phase lock loop high speed bypass mode | Gilles Dubost, Franck Dahan, Sylvain Dubois | 2012-10-02 |
| 8248867 | Memory cell employing reduced voltage | Donald George Mikan, Jr., Theodore W. Houston, Michael Patrick Clinton | 2012-08-21 |
| 8218376 | Reduced power consumption in retain-till-accessed static memories | Anand Seshadri | 2012-07-10 |
| 8207764 | Enhancement of power management using dynamic voltage and frequency scaling and digital phase lock loop high speed bypass mode | Gilles Dubost, Franck Dahan, Sylvain Dubois | 2012-06-26 |
| 8064275 | Local sensing and feedback for an SRAM array | Theodore W. Houston | 2011-11-22 |
| 8051313 | Apparatus, system and method of power state control | Bixia Li, Minh Chau, Alice Wang, Uming Ko | 2011-11-01 |