Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7650545 | Programmable interconnect for reconfigurable system-on-chip | Miron Abramovici, Yuzheng Ding, Barry Britton | 2010-01-19 |
| 7616029 | Hysteresis-based processing for applications such as signal bias monitors | William B. Andrews, Phillip Johnson, John Schadt | 2009-11-10 |
| 7554357 | Efficient configuration of daisy-chained programmable logic devices | Zheng Chen, Barry Britton | 2009-06-30 |
| 7429875 | Low static current drain logic circuit | Larry R. Fenstermaker | 2008-09-30 |
| 7414913 | Bitline twisting scheme for multiport memory | Larry R. Fenstermaker, Gregory S. Cartney, Allen White, Margaret Tait, Hemanshu T. Vernenker | 2008-08-19 |
| 7253674 | Output clock phase-alignment circuit | Phillip Johnson, Gary P. Powell | 2007-08-07 |
| 7196963 | Address isolation for user-defined configuration memory in programmable devices | Larry R. Fenstermaker, Sajitha Wijesuriya | 2007-03-27 |
| 7132903 | Noise-shielding, switch-controlled load circuitry for oscillators and the like | Phillip Johnson, Gary P. Powell | 2006-11-07 |
| 7034596 | Adaptive input logic for phase adjustments | William B. Andrews, Barry Britton | 2006-04-25 |
| 7009423 | Programmable I/O interfaces for FPGAs and other PLDs | William B. Andrews, Fulong Zhang | 2006-03-07 |
| 6952115 | Programmable I/O interfaces for FPGAs and other PLDs | William B. Andrews, Fulong Zhang | 2005-10-04 |
| 6943583 | Programmable I/O structure for FPGAs and the like having reduced pad capacitance | William B. Andrews, Mou C. Lin, Arifur Rahman | 2005-09-13 |
| 6873187 | Method and apparatus for controlling signal distribution in an electronic circuit | William B. Andrews, Barry Britton, Xiaotao Chen, John Philip Fishburn | 2005-03-29 |
| 6812869 | Noise reduction techniques for programmable input/output circuits | Arifur Rahman | 2004-11-02 |
| 6700823 | Programmable common mode termination for input/output circuits | Arifur Rahman | 2004-03-02 |
| 6486705 | Signal distribution scheme in field programmable gate array (FPGA) or field programmable system chip (FPSC) including cycle stealing units | William B. Andrews, Alfred E. Dunlop, John Philip Fishburn | 2002-11-26 |
| 6480026 | Multi-functional I/O buffers in a field programmable gate array (FPGA) | William B. Andrews | 2002-11-12 |