{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "AT&T", "item": "https://www.patentleaderboard.com/company/att"}, {"@type": "ListItem", "position": 3, "name": "Alfred E. Dunlop", "item": "https://www.patentleaderboard.com/inventor/fl:al_ln:dunlop-3"}]}
Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
AD

Alfred E. Dunlop — 14 Patents

ATAT&T: 9 patents #2,006 of 18,772Top 15%
ASAgere Systems: 1 patents #984 of 1,849Top 55%
AGAgere Systems Guardian: 1 patents #274 of 810Top 35%
DADafca: 1 patents #3 of 7Top 45%
LSLattice Semiconductor: 1 patents #317 of 544Top 60%
New Providence, NJ: #76 of 512 inventorsTop 15%
New Jersey: #6,230 of 69,400 inventorsTop 9%
Overall (All Time): #332,869 of 4,157,543Top 9%
14 Patents All Time
Alfred E. Dunlop has been granted 14 US patents while listed as an inventor at AT&T. The first was granted in 1986 and the most recent in July 2007. Alfred E. Dunlop ranks #332,869 of 4,157,543 US inventors in our database (top 8.0%). Patent records list Alfred E. Dunlop in New Providence, NJ, US.

Patents per Year

Patents granted per year, 1986 to 2007Bar chart with a peak of 3 patents in 2006.peak 31986: 1 patents19861989: 1 patents1993: 2 patents19931994: 1 patents1996: 1 patents19961998: 1 patents2001: 1 patents20012002: 1 patents2004: 1 patents20042006: 3 patents2007: 1 patents2007

Issued Patents All Time

Showing 1–14 of 14 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
7242739 Method and apparatus for multiphase, fast-locking clock and data recovery Glenn M. Boles, Manyalibo Joseph Matthews, Dusan Suvakovic, Doutje Van Veen 2007-07-10
7123675 Clock, data and time recovery using bit-resolved timing registers Glenn M. Boles, Ilija Hadzic, Manyalibo Joseph Matthews, Dusan Suvakovic, Doutje Van Veen 2006-10-17 $7,664,000
7058918 Reconfigurable fabric for SoCs using functional I/O leads Miron Abramovici 2006-06-06
7010077 Gated clock recovery circuit Wilhelm Fischer 2006-03-07 $3,032,000
6721872 Reconfigurable network interface architecture Asawaree Kalavade 2004-04-13 $10,278,000
6486705 Signal distribution scheme in field programmable gate array (FPGA) or field programmable system chip (FPSC) including cycle stealing units William B. Andrews, John Philip Fishburn, Harold Scholz 2002-11-26 $18,756,000
6259326 Clock recovery from a burst-mode digital signal each packet of which may have one of several predefined frequencies Wilhelm Fischer, Yusuke Ota 2001-07-10 $9,070,000
5757872 Clock recovery circuit Mihai Banu, Wilhelm Fischer, Thaddeus John Gabara, Kalpendu Shastri 1998-05-26 $23,982,000
5528199 Closed-loop frequency control of an oscillator circuit Wilhelm Fischer, Thaddeus John Gabara 1996-06-18
5298800 Digitally controlled element sizing Thaddeus John Gabara, Scott C. Knauer 1994-03-29
5237290 Method and apparatus for clock recovery Mihai Banu 1993-08-17
5194765 Digitally controlled element sizing Thaddeus John Gabara, Scott C. Knauer 1993-03-16
4827428 Transistor sizing system for integrated circuits John Philip Fishburn 1989-05-02
4577276 Placement of components on circuit substrates Brian W. Kernighan 1986-03-18