Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7242739 | Method and apparatus for multiphase, fast-locking clock and data recovery | Glenn M. Boles, Manyalibo Joseph Matthews, Dusan Suvakovic, Doutje Van Veen | 2007-07-10 |
| 7123675 | Clock, data and time recovery using bit-resolved timing registers | Glenn M. Boles, Ilija Hadzic, Manyalibo Joseph Matthews, Dusan Suvakovic, Doutje Van Veen | 2006-10-17 |
| 7058918 | Reconfigurable fabric for SoCs using functional I/O leads | Miron Abramovici | 2006-06-06 |
| 7010077 | Gated clock recovery circuit | Wilhelm Fischer | 2006-03-07 |
| 6721872 | Reconfigurable network interface architecture | Asawaree Kalavade | 2004-04-13 |
| 6486705 | Signal distribution scheme in field programmable gate array (FPGA) or field programmable system chip (FPSC) including cycle stealing units | William B. Andrews, John Philip Fishburn, Harold Scholz | 2002-11-26 |
| 6259326 | Clock recovery from a burst-mode digital signal each packet of which may have one of several predefined frequencies | Wilhelm Fischer, Yusuke Ota | 2001-07-10 |
| 5757872 | Clock recovery circuit | Mihai Banu, Wilhelm Fischer, Thaddeus John Gabara, Kalpendu Shastri | 1998-05-26 |
| 5528199 | Closed-loop frequency control of an oscillator circuit | Wilhelm Fischer, Thaddeus John Gabara | 1996-06-18 |
| 5298800 | Digitally controlled element sizing | Thaddeus John Gabara, Scott C. Knauer | 1994-03-29 |
| 5237290 | Method and apparatus for clock recovery | Mihai Banu | 1993-08-17 |
| 5194765 | Digitally controlled element sizing | Thaddeus John Gabara, Scott C. Knauer | 1993-03-16 |
| 4827428 | Transistor sizing system for integrated circuits | John Philip Fishburn | 1989-05-02 |
| 4577276 | Placement of components on circuit substrates | Brian W. Kernighan | 1986-03-18 |