Issued Patents All Time
Showing 1–25 of 37 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9772901 | Memory reliability using error-correcting code | Ravindraraj Ramaraju | 2017-09-26 |
| 9672938 | Memory with redundancy | Perry H. Pelley, Ravindraraj Ramaraju | 2017-06-06 |
| 9477548 | Error repair location cache | Ravindraraj Ramaraju | 2016-10-25 |
| 9425829 | Adaptive error correction codes (ECCs) for electronic memories | Ravindraraj Ramaraju | 2016-08-23 |
| 9396064 | Error correction with secondary memory | Ravindraraj Ramaraju | 2016-07-19 |
| 9389954 | Memory redundancy to replace addresses with multiple errors | Perry H. Pelley, Ravindraraj Ramaraju | 2016-07-12 |
| 9323602 | Error correction with extended CAM | Ravindraraj Ramaraju | 2016-04-26 |
| 9317087 | Memory column drowsy control | Ravindraraj Ramaraju, Jianan Yang, Mark W. Jetton, Thomas W. Liston, Andrew C. Russell | 2016-04-19 |
| 9224439 | Memory with word line access control | Ravindraraj Ramaraju, Andrew C. Russell | 2015-12-29 |
| 9225337 | Temperature threshold circuit with hysteresis | Perry H. Pelley, Ravindraraj Ramaraju | 2015-12-29 |
| 9208024 | Memory ECC with hard and soft error detection and management | Perry H. Pelley | 2015-12-08 |
| 9117498 | Memory with power savings for unnecessary reads | Ravindraraj Ramaraju, Andrew C. Russell | 2015-08-25 |
| 8487656 | Dynamic logic circuit | Ravindraraj Ramaraju | 2013-07-16 |
| 8487657 | Dynamic logic circuit | Ravindraraj Ramaraju, Maciej Bajkowski | 2013-07-16 |
| 8400859 | Dynamic random access memory (DRAM) refresh | Perry H. Pelley | 2013-03-19 |
| 8402327 | Memory system with error correction and method of operation | Perry H. Pelley, Peter J. Wilson | 2013-03-19 |
| 8090913 | Coherency groups of serially coupled processing cores propagating coherency information containing write packet to memory | Perry H. Pelley, Lucio F. C. Pessoa | 2012-01-03 |
| 7990795 | Dynamic random access memory (DRAM) refresh | Perry H. Pelley | 2011-08-02 |
| 7941637 | Groups of serially coupled processor cores propagating memory write packet while maintaining coherency within each group towards a switch coupled to memory partitions | Perry H. Pelley, Lucio F. C. Pessoa | 2011-05-10 |
| 7564738 | Double-rate memory | Perry H. Pelley | 2009-07-21 |
| 7443223 | Level shifting circuit | Maciej Bajkowski, Hamed Ghassemi | 2008-10-28 |
| 7362134 | Circuit and method for latch bypass | Maciej Bajkowski, Prashant U. Kenkare, Ravindraraj Ramaraju | 2008-04-22 |
| 7349266 | Memory device with a data hold latch | Ravindraraj Ramaraju, Prashant U. Kenkare | 2008-03-25 |
| 7185170 | Data processing system having translation lookaside buffer valid bits with lock and method therefor | Ravindraraj Ramaraju, David P. Burgess, Troy L. Cooper, Eric V. Fiene | 2007-02-27 |
| 7164293 | Dynamic latch having integral logic function and method therefor | Ravindraraj Ramaraju, Jeremiah Palmer | 2007-01-16 |