Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5597766 | Method for detaching chips from a wafer | — | 1997-01-28 |
| 5100811 | Integrated circuit containing bi-polar and complementary MOS transistors on a common substrate and method for the manufacture thereof | Josef Winnerl | 1992-03-31 |
| 5034338 | Circuit containing integrated bipolar and complementary MOS transistors on a common substrate | Josef Winnerl | 1991-07-23 |
| 5013678 | Method of making an integrated circuit comprising load resistors arranged on the field oxide zones which separate the active transistor zones | Josef Winnerl | 1991-05-07 |
| 4960489 | Method for self-aligned manufacture of contacts between interconnects contained in wiring levels arranged above one another in an integrated circuit | Guenther Roeska, Josef Winnerl | 1990-10-02 |
| 4912543 | Integrated semiconductor circuit having an external contacting track level consisting of aluminum or of an aluminum alloy | Ulrich Schwabe | 1990-03-27 |
| 4906585 | Method for manufacturing wells for CMOS transistor circuits separated by insulating trenches | Carlos Mazure-Espejo, Christoph Zeller | 1990-03-06 |
| 4885617 | Metal-oxide semiconductor (MOS) field effect transistor having extremely shallow source/drain zones and silicide terminal zones, and a process for producing the transistor circuit | C. A. Mazure-Espejo | 1989-12-05 |
| 4884117 | Circuit containing integrated bipolar and complementary MOS transistors on a common substrate | Josef Winnerl | 1989-11-28 |
| 4874717 | Semiconductor circuit containing integrated bipolar and MOS transistors on a chip and method of producing same | Ulrich Schwabe | 1989-10-17 |
| 4855245 | Method of manufacturing integrated circuit containing bipolar and complementary MOS transistors on a common substrate | Josef Winnerl | 1989-08-08 |
| 4803179 | Methods for making neighboring wells for VLS1 CMOS components | Carlos-Alberto Mazure-Espejo | 1989-02-07 |
| 4782033 | Process for producing CMOS having doped polysilicon gate by outdiffusion of boron from implanted silicide gate | Heike Gierisch | 1988-11-01 |
| 4761384 | Forming retrograde twin wells by outdiffusion of impurity ions in epitaxial layer followed by CMOS device processing | Erwin Jacobs, Josef Winnerl, Carlos-Alberto Mazure-Espejo | 1988-08-02 |
| 4740479 | Method for the manufacture of cross-couplings between n-channel and p-channel CMOS field effect transistors of static write-read memories | Konrad Hieber, Ulrich Schwabe | 1988-04-26 |
| 4680612 | Integrated semiconductor circuit including a tantalum silicide diffusion barrier | Konrad Hieber, Konrad Schober | 1987-07-14 |
| 4673968 | Integrated MOS transistors having a gate metallization composed of tantalum or niobium or their silicides | Konrad Hieber | 1987-06-16 |
| 4640844 | Method for the manufacture of gate electrodes formed of double layers of metal silicides having a high melting point and doped polycrystalline silicon | Ulrich Schwabe, Konrad Hieber | 1987-02-03 |
| 4603472 | Method of making MOS FETs using silicate glass layer as gate edge masking for ion implantation | Ulrich Schwabe, Erwin Jacobs | 1986-08-05 |
| 4525378 | Method for manufacturing VLSI complementary MOS field effect circuits | Ulrich Schwabe, Erwin Jacobs | 1985-06-25 |
| 4510670 | Method for the manufacture of integrated MOS-field effect transistor circuits silicon gate technology having diffusion zones coated with silicide as low-impedance printed conductors | Ulrich Schwabe, Konrad Hieber | 1985-04-16 |
| 4505027 | Method of making MOS device using metal silicides or polysilicon for gates and impurity source for active regions | Ulrich Schwabe, Ulf Burker, Werner Christoph | 1985-03-19 |