Issued Patents All Time
Showing 1–25 of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9473172 | Receiver deserializer latency trim | Leonard R. Chieco, Michael A. Sorna | 2016-10-18 |
| 9374098 | Transmitter serializer latency trim | Leonard R. Chieco, Michael A. Sorna | 2016-06-21 |
| 8587464 | Off-line gain calibration in a time-interleaved analog-to-digital converter | Anthony R. Bonaccio, Martin Schmatz, Benjamin T. Voegli | 2013-11-19 |
| 8493250 | Comparator offset cancellation in a successive approximation analog-to-digital converter | Anthony R. Bonaccio, Benjamin T. Voegeli | 2013-07-23 |
| 6941435 | Integrated circuit having register configuration sets | Anthony R. Bonaccio, Robert E. Busch, Barton E. Green, Troy A. Seman | 2005-09-06 |
| 6934103 | Read channel with automatic servo track writer | Valerie H. Chickanosky | 2005-08-23 |
| 6373906 | Method and apparatus for Viterbi detection of generalized partial response signals including two-way add/compare/select for improved channel speed | Roy D. Cideciyan, Jonathan Darrel Coker, Evangelos S. Eleftheriou, Richard Leo Galbraith, Allen Haar +1 more | 2002-04-16 |
| 6233191 | Field programmable memory array | Scott Whitney Gould, Joseph A. Iadanza | 2001-05-15 |
| 6130854 | Programmable address decoder for field programmable memory array | Scott Whitney Gould, Joseph A. Iadanza, Terrance John Zittritsch | 2000-10-10 |
| 6118707 | Method of operating a field programmable memory array with a field programmable gate array | Scott Whitney Gould, Joseph A. Iadanza, Terrance John Zittritsch | 2000-09-12 |
| 6075745 | Field programmable memory array | Scott Whitney Gould, Joseph A. Iadanza, Victor Paul Seidel, Terrance John Zittritsch | 2000-06-13 |
| 6044031 | Programmable bit line drive modes for memory arrays | Joseph A. Iadanza | 2000-03-28 |
| 6038192 | Memory cells for field programmable memory array | Kim P. N. Clinton, Joseph A. Iadanza, Victor Paul Seidel, Terrance John Zittritsch | 2000-03-14 |
| 6023421 | Selective connectivity between memory sub-arrays and a hierarchical bit line structure in a memory array | Kim P. N. Clinton, Scott Whitney Gould, Joseph A. Iadanza, Ralph David Kilmoyer, Michael Joseph Laramie +2 more | 2000-02-08 |
| 6021513 | Testable programmable gate array and associated LSSD/deterministic test methodology | Wayne Kevin Beebe, Sally Botala, Scott Whitney Gould, Wendell Ray Larsen, Ronald Raymond Palmer +1 more | 2000-02-01 |
| 5949719 | Field programmable memory array | Kim P. N. Clinton, Scott Whitney Gould, Joseph A. Iadanza, Ralph David Kilmoyer, Michael Joseph Laramie +2 more | 1999-09-07 |
| 5802003 | System for implementing write, initialization, and reset in a memory array using a single cell write port | Joseph A. Iadanza, Ralph David Kilmoyer, Michael Joseph Laramie | 1998-09-01 |
| 5781032 | Programmable inverter circuit used in a programmable logic cell | Allan Robert Bertolet, Kim P. N. Clinton, Christine Marie Fuller, Scott Whitney Gould, Steven Paul Hartman +6 more | 1998-07-14 |
| 5748009 | Programmable logic cell | Allan Robert Bertolet, Kim P. N. Clinton, Christine Marie Fuller, Scott Whitney Gould, Steven Paul Hartman +6 more | 1998-05-05 |
| 5745734 | Method and system for programming a gate array using a compressed configuration bit stream | David Craft, Scott Whitney Gould, Brian Worth | 1998-04-28 |
| 5734582 | Method and system for layout and schematic generation for heterogeneous arrays | Allan Robert Bertolet, Kim P. N. Clinton, Scott Whitney Gould, Timothy Shawn Reny, Terrance John Zittritsch | 1998-03-31 |
| 5732246 | Programmable array interconnect latch | Scott Whitney Gould, Wendell Ray Larsen, Brian Worth | 1998-03-24 |
| 5717346 | Low skew multiplexer network and programmable array clock/reset application thereof | Scott Whitney Gould, Frederick Curtis Furtek, Brian Worth, Terrance John Zittritsch | 1998-02-10 |
| 5703498 | Programmable array clock/reset resource | Scott Whitney Gould, Frederick Curtis Furtek, Brian Worth, Terrance John Zittritsch | 1997-12-30 |
| 5692147 | Memory mapping method and apparatus to fold sparsely populated structures into densely populated memory columns or rows by selectively transposing X and Y address portions, and programmable gate array applications thereof | Wendell Ray Larsen, Brian Worth | 1997-11-25 |