EY

Erwin E. Yu

Micron: 20 patents #865 of 6,345Top 15%
IN Intel: 4 patents #8,473 of 30,777Top 30%
Overall (All Time): #168,000 of 4,157,543Top 5%
24
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12276686 Apparatus for determination of capacitive and resistive characteristics of access lines Dan Xu, Jun Xu 2025-04-15
12183396 Memory array structures and methods of forming memory array structures Dan Xu, Jun Xu, Paolo Tessariol, Tomoko Ogura Iwasaki 2024-12-31
12171096 Microelectronic devices, and related memory devices and electronic systems Michele Piccardi, Surendranath C. Eruvuru 2024-12-17
12101932 Microelectronic devices, and related memory devices and electronic systems Surendranath C. Eruvuru, Yoshiaki Fukuzumi, Tomoko Ogura Iwasaki 2024-09-24
12068037 Managing sub-block erase operations in a memory sub-system Kalyan C. Kavalipurapu, Tomoko Ogura Iwasaki, Hong-Yan Chen, Yunfei Xu 2024-08-20
11942159 Selective management of erase operations in memory devices that enable suspend commands Chulbum Kim, Brian Kwon, Kitae Park, Taehyun Kim 2024-03-26
11915758 Memory devices with four data line bias levels Hao Thai Nguyen, Tomoko Ogura Iwasaki, Dheeraj Srinivasan, Sheyang Ning, Lawrence Celso Miranda +2 more 2024-02-27
11862257 Managing programming convergence associated with memory cells of a memory sub-system Jun Xu, Violante Moschiano 2024-01-02
11749353 Managing sub-block erase operations in a memory sub-system Kalyan C. Kavalipurapu, Tomoko Ogura Iwasaki, Hong-Yan Chen, Yunfei Xu 2023-09-05
11562791 Memory devices with four data line bias levels Hao Thai Nguyen, Tomoko Ogura Iwasaki, Dheeraj Srinivasan, Sheyang Ning, Lawrence Celso Miranda +2 more 2023-01-24
11557351 Sense circuit to sense two states of a memory cell Luyen Vu, Jeffrey Ming-Hung Tsai 2023-01-17
11557341 Memory array structures and methods for determination of resistive characteristics of access lines Dan Xu, Jun Xu, Paolo Tessariol, Tomoko Ogura Iwasaki 2023-01-17
11532367 Managing programming convergence associated with memory cells of a memory sub-system Jun Xu, Violante Moschiano 2022-12-20
11442091 Apparatus and methods for determination of capacitive and resistive characteristics of access lines Dan Xu, Jun Xu 2022-09-13
11335412 Managing sub-block erase operations in a memory sub-system Kalyan C. Kavalipurapu, Tomoko Ogura Iwasaki, Hong-Yan Chen, Yunfei Xu 2022-05-17
10790029 Temperature compensation in memory sensing Luyen Vu, Kalyan C. Kavalipurau, Jae-Kwan Park 2020-09-29
10163500 Sense matching for hard and soft memory reads William C. Filipiak, Dheeraj Srinivasan 2018-12-25
10127988 Temperature compensation in memory sensing Luyen Vu, Kalyan C. Kavalipurau, Jae-Kwan Park 2018-11-13
10049759 Reducing verification checks when programming a memory device Kalyan C. Kavalipurapu, Allahyar Vahidimowlavi 2018-08-14
9842655 Reducing verification checks when programming a memory device Kalyan C. Kavalipurapu, Allahyar Vahidimowlavi 2017-12-12
9633744 On demand knockout of coarse sensing based on dynamic source bounce detection Kalyan C. Kavalipurapu, Jae-Kwan Park, Michele Piccardi 2017-04-25
8179726 Method and apparatus for programming flash memory Ebrahim Abedifard, Frederick T. Jaffin, Uday Chandrasekhar 2012-05-15
7974129 Method and apparatus for programming flash memory Ebrahim Abedifard, Frederick T. Jaffin, Uday Chandrasekhar 2011-07-05
7663925 Method and apparatus for programming flash memory Ebrahim Abedifard, Frederick T. Jaffin, Uday Chandrasekhar 2010-02-16