Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10198382 | 12C bus controller slave address register and command FIFO buffer | Frederic Danis | 2019-02-05 |
| 9336167 | I2C controller register, control, command and R/W buffer queue logic | Frederic Danis | 2016-05-10 |
| 9264217 | Clock drift compensation applying paired clock compensation values to buffer | Laurent Le-Faucheur | 2016-02-16 |
| 9014321 | Clock drift compensation interpolator adjusting buffer read and write clocks | Laurent Le Faucheur | 2015-04-21 |
| 8699953 | Low-latency interface-based networking | Yves Masse, Philippe Gentric | 2014-04-15 |
| 8190861 | Micro-sequence based security model | Gerard Chauvel, Gilbert Cabillic, Jean-Philippe Lesot, Dominique D'Inverno, Serge Lasserre | 2012-05-29 |
| 8190794 | Control function for memory based buffers | Laurent Le Faucheur | 2012-05-29 |
| 8156283 | Processing function connected to processor memory hierarchy | Serge Lasserre | 2012-04-10 |
| 7234034 | Self-clocking memory device | Stephen Wayne Spriggs, Vikas Agrawal, Bryan Sheffield | 2007-06-19 |
| 7200730 | Method of operating a memory at high speed using a cycle ready status output signal | Bryan Sheffield, Vikas Agrawal, Stephen Wayne Spriggs | 2007-04-03 |
| 7139854 | Pipelining access to serialization tokens on a bus | Jonathan Yu Zhang, Robert Nychka | 2006-11-21 |
| 7035985 | Method and apparatus for accessing a memory core multiple times in a single clock cycle | Jean Bachot | 2006-04-25 |
| 6658578 | Microprocessors | Gilbert Laurenti, Jean-Pierre Giacalone, Emmanuel Ego, Anne Lombardot, Francois Theodorou +20 more | 2003-12-02 |
| 6629223 | Method and apparatus for accessing a memory core multiple times in a single clock cycle | Jean Bachot | 2003-09-30 |