Issued Patents All Time
Showing 1–25 of 41 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8539159 | Dirty cache line write back policy based on stack size trend information | Gerard Chauvel, Serge Lasserre | 2013-09-17 |
| 8429383 | Multi-processor computing system having a JAVA stack machine and a RISC-based processor | Gerard Chauvel, Serge Lasserre, Maija Kuusela | 2013-04-23 |
| 8190861 | Micro-sequence based security model | Gerard Chauvel, Gilbert Cabillic, Jean-Philippe Lesot, Eric Louis Pierre Badi, Serge Lasserre | 2012-05-29 |
| 8032891 | Energy-aware scheduling of application execution | Gerard Chauvel, Serge Lasserre, Maija Kuusela, Gilbert Cabillic, Jean-Philippe Lesot +4 more | 2011-10-04 |
| 7941790 | Data processing apparatus, system and method | Gilbert Cabillic, Jean-Philippe Lesot, Michel Banatre, Gerard Chauvel, Teresa Higuera +4 more | 2011-05-10 |
| 7840782 | Mixed stack-based RISC processor | Gerard Chauvel, Serge Lasserre | 2010-11-23 |
| 7840784 | Test and skip processor instruction having at least one register operand | Gerard Chauvel, Serge Lasserre | 2010-11-23 |
| 7716673 | Tasks distribution in a multi-processor including a translation lookaside buffer shared between processors | Gerard Chauvel | 2010-05-11 |
| 7634643 | Stack register reference control bit in source operand of instruction | Gerard Chauvel, Serge Lasserre | 2009-12-15 |
| 7565385 | Embedded garbage collection | Gerard Chauvel, Serge Lasserre, Maija Kuusela, Gilbert Cabillic, Jean-Philippe Lesot +4 more | 2009-07-21 |
| 7543014 | Saturated arithmetic in a processing unit | Gerard Chauvel | 2009-06-02 |
| 7509391 | Unified memory management system for multi processor heterogeneous architecture | Gerard Chauvel, Serge Lasserre | 2009-03-24 |
| 7496930 | Accessing device driver memory in programming language representation | Gerard Chauvel, Serge Lasserre, Maija Kuusela, Gilbert Cabillic, Jean-Philippe Lesot +4 more | 2009-02-24 |
| 7434021 | Memory allocation in a multi-processor system | Gerard Chauvel, Serge Lasserre, Maija Kuusela, Gilbert Cabillic, Jean-Philippe Lesot +4 more | 2008-10-07 |
| 7386671 | Smart cache | Gerard Chauvel, Serge Lasserre | 2008-06-10 |
| 7330937 | Management of stack-based memory usage in a processor | Gerard Chauvel, Serge Lasserre, Maija Kuusela, Gilbert Cabillic, Jean-Philippe Lesot +4 more | 2008-02-12 |
| 7203797 | Memory management of local variables | Gerard Chauvel, Maija Kuusela | 2007-04-10 |
| 7174194 | Temperature field controlled scheduling for processing systems | Gerard Chauvel, Darvin R. Edwards | 2007-02-06 |
| 7146613 | JAVA DSP acceleration by byte-code optimization | Gerard Chauvel | 2006-12-05 |
| 7120715 | Priority arbitration based on current task and MMU | Gerard Chauvel | 2006-10-10 |
| 7111177 | System and method for executing tasks according to a selected scenario in response to probabilistic power consumption information of each scenario | Gerard Chauvel | 2006-09-19 |
| 7069415 | System and method to automatically stack and unstack Java local variables | Gerard Chauvel, Maija Kuusela | 2006-06-27 |
| 7062304 | Task based adaptative profiling and debugging | Gerard Chauvel | 2006-06-13 |
| 6996683 | Cache coherency in a multi-processor system | Gerard Chauvel, Serge Lasserre, Maija Kuusela | 2006-02-07 |
| 6934820 | Traffic controller using priority and burst control for reducing access latency | Gerard Chauvel, Serge Lasserre | 2005-08-23 |