Issued Patents All Time
Showing 26–41 of 41 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6901521 | Dynamic hardware control for energy management systems using task attributes | Gerard Chauvel | 2005-05-31 |
| 6889330 | Dynamic hardware configuration for energy management systems using task attributes | Gerard Chauvel | 2005-05-03 |
| 6826652 | Smart cache | Gerard Chauvel, Serge Lasserre | 2004-11-30 |
| 6792508 | Cache with multiple fill modes | Gerard Chauvel, Serge Lasserre | 2004-09-14 |
| 6772326 | Interruptible an re-entrant cache clean range instruction | Gerard Chauvel, Serge Lasserre | 2004-08-03 |
| 6769052 | Cache with selective write allocation | Gerard Chauvel, Maija Kuusela | 2004-07-27 |
| 6760829 | MMU descriptor having big/little endian bit to control the transfer data between devices | Serge Lasserre, Gerard Chauvel | 2004-07-06 |
| 6751706 | Multiple microprocessors with a shared cache | Gerard Chauvel, Maija Kuusela, Serge Lasserre | 2004-06-15 |
| 6742104 | Master/slave processing system with shared translation lookaside buffer | Gerard Chauvel, Serge Lasserre | 2004-05-25 |
| 6742103 | Processing system with shared translation lookaside buffer | Gerard Chauvel, Serge Lasserre | 2004-05-25 |
| 6681297 | Software controlled cache configuration based on average miss rate | Gerard Chauvel, Serge Lasserre | 2004-01-20 |
| 6606687 | Optimized hardware cleaning function for VIVT data cache | Gerard Chauvel, Serge Lasserre | 2003-08-12 |
| 6430664 | Digital signal processor with direct and virtual addressing | Gerard Chauvel, Serge Lasserre | 2002-08-06 |
| 6412048 | Traffic controller using priority and burst control for reducing access latency | Gerard Chauvel, Serge Lasserre | 2002-06-25 |
| 6321299 | Computer circuits, systems, and methods using partial cache cleaning | Gerard Chauvel, Serge Lasserre | 2001-11-20 |
| 6253297 | Memory control using memory state information for reducing access latency | Gerard Chauvel, Serge Lasserre | 2001-06-26 |