Issued Patents All Time
Showing 25 most recent of 117 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8782675 | Method and system of accessing display window memory | Gilbert Cabillic | 2014-07-15 |
| 8539159 | Dirty cache line write back policy based on stack size trend information | Serge Lasserre, Dominique D'Inverno | 2013-09-17 |
| 8516502 | Performing java interrupt with two program counters | Gilbert Cabillic, Jean-Philippe Lesot | 2013-08-20 |
| 8516496 | Storing contexts for thread switching | Gilbert Cabillic | 2013-08-20 |
| 8489860 | Mobile electronic device having a host processor system capable of dynamically canging tasks performed by a coprocessor in the device | Michael T. McMahon, Marion C. Lineberry, Matthew A. Woolsey | 2013-07-16 |
| 8429383 | Multi-processor computing system having a JAVA stack machine and a RISC-based processor | Serge Lasserre, Maija Kuusela, Dominique D'Inverno | 2013-04-23 |
| 8190861 | Micro-sequence based security model | Gilbert Cabillic, Jean-Philippe Lesot, Dominique D'Inverno, Eric Louis Pierre Badi, Serge Lasserre | 2012-05-29 |
| 8185666 | Compare instruction | — | 2012-05-22 |
| 8078842 | Removing local RAM size limitations when executing software code | Gilbert Cabillic, Jean-Philippe Lesot | 2011-12-13 |
| 8046748 | Method and system to emulate an M-bit instruction set | Gilbert Cabillic, Jean-Philippe Lesot | 2011-10-25 |
| 8032891 | Energy-aware scheduling of application execution | Dominique D'Inverno, Serge Lasserre, Maija Kuusela, Gilbert Cabillic, Jean-Philippe Lesot +4 more | 2011-10-04 |
| 8024554 | Modifying an instruction stream using one or more bits to replace an instruction or to replace an instruction and to subsequently execute the replaced instruction | — | 2011-09-20 |
| 7941790 | Data processing apparatus, system and method | Gilbert Cabillic, Jean-Philippe Lesot, Michel Banatre, Dominique D'Inverno, Teresa Higuera +4 more | 2011-05-10 |
| 7930689 | Method and system for accessing indirect memories | Gilbert Cabillic, Jean-Philippe Lesot | 2011-04-19 |
| 7840782 | Mixed stack-based RISC processor | Serge Lasserre, Dominique D'Inverno | 2010-11-23 |
| 7840784 | Test and skip processor instruction having at least one register operand | Serge Lasserre, Dominique D'Inverno | 2010-11-23 |
| 7757223 | Method and system to construct a data-flow analyzer for a bytecode verifier | Gilbert Cabillic, Jean-Philippe Lesot, Mikael Peltier | 2010-07-13 |
| 7757067 | Pre-decoding bytecode prefixes selectively incrementing stack machine program counter | Serge Lasserre, Maija Kuusela | 2010-07-13 |
| 7743384 | Method and system for implementing an interrupt handler | Gilbert Cabillic, Jean-Philippe Lesot | 2010-06-22 |
| 7716673 | Tasks distribution in a multi-processor including a translation lookaside buffer shared between processors | Dominique D'Inverno | 2010-05-11 |
| 7712098 | Data transfer controlled by task attributes | Serge Lasserre, Edward Ferguson | 2010-05-04 |
| 7634643 | Stack register reference control bit in source operand of instruction | Serge Lasserre, Dominique D'Inverno | 2009-12-15 |
| 7624382 | Method and system of control flow graph construction | Jean-Philippe Lesot, Gilbert Cabillic, Mikael Peltier | 2009-11-24 |
| 7587583 | Method and system for processing a “WIDE” opcode when it is not used as a prefix for an immediately following opcode | — | 2009-09-08 |
| 7574584 | Splitting execution of a floating-point add instruction between an integer pipeline for performing mantissa addition and a hardware state machine | Maija Kuusela | 2009-08-11 |