Issued Patents All Time
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5749090 | Cache tag RAM having separate valid bit array with multiple step invalidation and method therefor | Taisheng Feng | 1998-05-05 |
| 5670815 | Layout for noise reduction on a reference voltage | Lawrence F. Childs, Stephen T. Flannagan, Ray L. Chang | 1997-09-23 |
| 5546355 | Integrated circuit memory having a self-timed write pulse independent of clock frequency and duty cycle | Taisheng Feng | 1996-08-13 |
| 5497106 | BICMOS output buffer circuit having overshoot protection | Taisheng Feng, Alan R. Bormann | 1996-03-05 |
| 5477176 | Power-on reset circuit for preventing multiple word line selections during power-up of an integrated circuit memory | Ray L. Chang, Lawrence F. Childs, Kenneth W. Jones, Stephen T. Flannagan | 1995-12-19 |
| 5333119 | Digital signal processor with delayed-evaluation array multipliers and low-power memory addressing | Gerald E. Sobelman | 1994-07-26 |