Issued Patents All Time
Showing 25 most recent of 42 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12353333 | Pre-fetching address translation for computation offloading | Aditya Madhusudan DESHPANDE, Manisha GAJBE, Arun RODRIGUES | 2025-07-08 |
| 12316537 | Multi-dimensional routing architecture | Alejandro Rico Carro, Saurabh Sinha, Tiago Rogerio Muck | 2025-05-27 |
| 11954040 | Cache memory architecture | Alejandro Rico Carro, Saurabh Sinha | 2024-04-09 |
| 11169848 | Power aware scheduling of requests in 3D chip stack | Philip Jacob, James P. Coghlan, Michael Grassi, Kirk Pospesel, Marcel Schaal | 2021-11-09 |
| 10740116 | Three-dimensional chip-based regular expression scanner | Jan Van Lunteren, James P. Coghlan | 2020-08-11 |
| 10579425 | Power aware scheduling of requests in 3D chip stack | Philip Jacob, James P. Coghlan, Michael Grassi, Kirk Pospesel, Marcel Schaal | 2020-03-03 |
| 9684629 | Efficient calibration of a low power parallel data communications channel | Timothy O. Dickson, Daniel M. Dreps, Frank D. Ferraiolo | 2017-06-20 |
| 9411750 | Efficient calibration of a low power parallel data communications channel | Timothy O. Dickson, Daniel M. Dreps, Frank D. Ferraiolo | 2016-08-09 |
| 9298395 | Memory system connector | Paul W. Coteus, Shawn A. Hall, Hillery C. Hunter, Charles A. Kilmer, Kyu-hyoun Kim +2 more | 2016-03-29 |
| 9053811 | Memory device refresh | Paul W. Coteus, Kyu-hyoun Kim | 2015-06-09 |
| 9001842 | Parallel receiver interface with receiver redundancy | Timothy O. Dickson, Frank D. Ferraiolo | 2015-04-07 |
| 8949685 | Soft error protection in individual memory devices | Mark B. Ritter, Jose A. Tierno | 2015-02-03 |
| 8311051 | Use of hardware to manage dependencies between groups of network data packets | Douglas G. Balazich, Carl A. Bender, Peter K. Szwed | 2012-11-13 |
| 8229916 | Method for massively parallel multi-core text indexing | Ankur Narang, Vikas Agarwal, Vijay Garg, Monu Kedia, Maged M. Michael | 2012-07-24 |
| 8138015 | Interconnection in multi-chip with interposers and bridges | John U. Knickerbocker | 2012-03-20 |
| 8008764 | Bridges for interconnecting interposers in multi-chip integrated circuits | John U. Knickerbocker | 2011-08-30 |
| 7912988 | Receive queue device with efficient queue flow control, segment placement and virtualization mechanisms | William T. Boyd, Jean Calvignac, Chih-jen Chang, Renato J. Recio | 2011-03-22 |
| 7818362 | Split socket send queue apparatus and method with efficient queue flow control, retransmission and sack support mechanisms | William T. Boyd, Jean Calvignac, Chih-jen Chang, Renato J. Recio | 2010-10-19 |
| 7724757 | Use of hardware to manage dependencies between groups of network data packets | Douglas G. Balazich, Carl A. Bender, Peter K. Szwed | 2010-05-25 |
| 7721182 | Soft error protection in individual memory devices | Mark B. Ritter, Jose A. Tierno | 2010-05-18 |
| 7519650 | Split socket send queue apparatus and method with efficient queue flow control, retransmission and sack support mechanisms | William T. Boyd, Jean Calvignac, Chih-jen Chang, Renato J. Recio | 2009-04-14 |
| 7408945 | Use of hardware to manage dependencies between groups of network data packets | Douglas G. Balazich, Carl A. Bender, Peter K. Szwed | 2008-08-05 |
| 7353429 | System and method using hardware buffers for processing microcode trace data | Walker Carroll, Gabriel M. Tarr | 2008-04-01 |
| 7299266 | Memory management offload for RDMA enabled network adapters | William T. Boyd, Michael A. Ko, Renato J. Recio | 2007-11-20 |
| 7099997 | Read-modify-write avoidance using a boundary word storage mechanism | Douglas G. Balazich, Peter K. Szwed, Carl A. Bender | 2006-08-29 |