Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10488062 | Geofence plus schedule for a building controller | David Quam, Sara Slate, Ted Booth, Shannon Roberts, Jason Tiefenauer | 2019-11-26 |
| 10302322 | Triage of initial schedule setup for an HVAC controller | David Quam, Sara Slate, Ted Booth, Shannon Roberts, Jason Tiefenauer | 2019-05-28 |
| 5809533 | Dual bus system with multiple processors having data coherency maintenance | Paul B. Ricci, Jayesh V. Sheth, Theodore C. White, Richard A. Cowgill | 1998-09-15 |
| 5666515 | Information processing system having multiple modules and a memory on a bus, where any module can lock an addressable portion of the memory by sending retry signals to other modules that try to read at the locked address | Theodore C. White, Jayesh V. Sheth, Kha Nguyen | 1997-09-09 |
| 5598421 | Method and system for tracking the state of each one of multiple JTAG chains used in testing the logic of intergrated circuits | Wayne C. Datwyler, Long Ha | 1997-01-28 |
| 5553249 | Dual bus adaptable data path interface system | Wayne C. Datwyler, Long Ha | 1996-09-03 |
| 5511224 | Configurable network using dual system busses with common protocol compatible for store-through and non-store-through cache memories | Paul B. Ricci, Jayesh V. Sheth, Theodore C. White, Richard A. Cowgill | 1996-04-23 |
| 5495573 | Error logging system with clock rate translation | Wayne C. Datwyler, Long Ha | 1996-02-27 |
| 5444722 | Memory module with address error detection | — | 1995-08-22 |
| 5293496 | Inhibit write apparatus and method for preventing bus lockout | Theodore C. White, Jayesh V. Sheth, Paul B. Ricci | 1994-03-08 |
| 5293621 | Varying wait interval retry apparatus and method for preventing bus lockout | Theodore C. White, Jayesh V. Sheth, Paul B. Ricci | 1994-03-08 |