Issued Patents All Time
Showing 1–25 of 37 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11362645 | Power managers for an integrated circuit | Barry A. Hoberman, Jon Shiell | 2022-06-14 |
| 10749506 | Power managers for an integrated circuit | Barry A. Hoberman, Jon Shiell | 2020-08-18 |
| 10628316 | Memory device with a plurality of memory banks where each memory bank is associated with a corresponding memory instruction pipeline and a dynamic redundancy register | Neal Berger, Benjamin Louie, Mourad El-Baraji, Lester Crudele | 2020-04-21 |
| 10460781 | Memory device with a dual Y-multiplexer structure for performing two simultaneous operations on the same row of a memory bank | Neal Berger, Benjamin Louie, Mourad El-Baraji, Lester Crudele | 2019-10-29 |
| 10446210 | Memory instruction pipeline with a pre-read stage for a write operation for reducing power consumption in a memory device that uses dynamic redundancy registers | Neal Berger, Benjamin Louie, Mourad El-Baraji, Lester Crudele | 2019-10-15 |
| 10437491 | Method of processing incomplete memory operations in a memory device during a power up sequence and a power down sequence using a dynamic redundancy register | Neal Berger, Benjamin Louie, Mourad El-Baraji, Lester Crudele | 2019-10-08 |
| 10437723 | Method of flushing the contents of a dynamic redundancy register to a secure storage area during a power down in a memory device | Neal Berger, Benjamin Louie, Mourad El-Baraji, Lester Crudele | 2019-10-08 |
| 10424393 | Method of reading data from a memory device using multiple levels of dynamic redundancy registers | Mourad El Baraji, Neal Berger, Benjamin Louie, Lester Crudele, Barry A. Hoberman | 2019-09-24 |
| 10366774 | Device with dynamic redundancy registers | Mourad El Baraji, Neal Berger, Benjamin Louie, Lester Crudele, Barry A. Hoberman | 2019-07-30 |
| 10366775 | Memory device using levels of dynamic redundancy registers for writing a data word that failed a write operation | Mourad El-Baraji, Neal Berger, Benjamin Louie, Lester Crudele, Barry A. Hoberman | 2019-07-30 |
| 10360964 | Method of writing contents in memory during a power up sequence using a dynamic redundancy register in a memory device | Neal Berger, Benjamin Louie, Mourad El-Baraji, Lester Crudele | 2019-07-23 |
| 10243542 | Power managers for an integrated circuit | Barry A. Hoberman, Jon Shiell | 2019-03-26 |
| 10192602 | Smart cache design to prevent overflow for a memory device with a dynamic redundancy register | Neal Berger, Benjamin Louie, Mourad El-Baraji, Lester Crudele | 2019-01-29 |
| 10192601 | Memory instruction pipeline with an additional write stage in a memory device that uses dynamic redundancy registers | Neal Berger, Benjamin Louie, Mourad El-Baraji, Lester Crudele | 2019-01-29 |
| 9722605 | Low leakage and data retention circuitry | Barry A. Hoberman, William G. Walker, John M. Callahan, Michael A. Zampaglione, Andrew Cole | 2017-08-01 |
| 9660616 | Power managers for an integrated circuit | Barry A. Hoberman, Jon Shiell | 2017-05-23 |
| 9350349 | Low leakage and data retention circuitry | Barry A. Hoberman, William G. Walker, John M. Callahan, Michael A. Zampaglione, Andrew Cole | 2016-05-24 |
| 9166412 | Power managers for an integrated circuit | Barry A. Hoberman, Jon Shiell | 2015-10-20 |
| 8854077 | Low leakage and data retention circuitry | Barry A. Hoberman, William G. Walker, John M. Callahan, Michael A. Zampaglione, Andrew Cole | 2014-10-07 |
| 8782590 | Power managers for an integrated circuit | Barry A. Hoberman, Jon Shiell | 2014-07-15 |
| 8762923 | Power managers for an integrated circuit | Barry A. Hoberman, Jon Shiell | 2014-06-24 |
| 8253438 | Low leakage and data retention circuitry | Barry A. Hoberman, William G. Walker, John M. Callahan, Michael A. Zampaglione, Andrew Cole | 2012-08-28 |
| 8026738 | Integrated circuit with signal bus formed by cell abutment of logic cells | William G. Walker | 2011-09-27 |
| 7996811 | Power managers for an integrated circuit | Barry A. Hoberman, Jon Shiell | 2011-08-09 |
| 7945885 | Power managers for an integrated circuit | Barry A. Hoberman, Jon Shiell | 2011-05-17 |