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Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
DD

David W. Daniel — 18 Patents

LSLsi: 16 patents #173 of 3,238Top 6%
NINationwide Mutual Insurance: 1 patents #55 of 92Top 60%
SYSymbios: 1 patents #17 of 39Top 45%
Divide, CO: #6 of 32 inventorsTop 20%
Colorado: #2,271 of 40,980 inventorsTop 6%
Overall (All Time): #245,716 of 4,157,543Top 6%
18 Patents All Time
David W. Daniel has been granted 18 US patents. The first was granted in 1999 and the most recent in August 2021. David W. Daniel ranks #245,716 of 4,157,543 US inventors in our database (top 5.9%). Patent records list David W. Daniel in Divide, CO, US.

Patents per Year

Patents granted per year, 1999 to 2021Bar chart with a peak of 4 patents in 2000.peak 41999: 2 patents19992000: 4 patents20002001: 4 patents20012002: 3 patents20022003: 1 patents20032005: 2 patents20052006: 1 patents20062021: 1 patents2021

Issued Patents All Time

Showing 1–18 of 18 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
11095675 System and method for identifying system vulnerabilities David Clark, Kevin J. Sullivan, Jane L M Kuberski, Paul J. Melko, Jr., Narayanasamy Balakrishnan +4 more 2021-08-17
7095483 Process independent alignment marks James R. B. Elmer 2006-08-22 $3,850,000
6870160 Method and apparatus for monitoring the condition of a lubricating medium 2005-03-22 $2,090,000
6856029 Process independent alignment marks James R. B. Elmer 2005-02-15 $5,122,000
6506684 Anti-corrosion system Dodd Defibaugh 2003-01-14 $5,401,000
6372520 Sonic assisted strengthening of gate oxides Kang-Jay Hsia, George H. Maggard 2002-04-16 $20,336,000
6354908 Method and apparatus for detecting a planarized outer layer of a semiconductor wafer with a confocal optical system Derryl D. J. Allman, John Gregory 2002-03-12 $24,274,000
6355532 Subtractive oxidation method of fabricating a short-length and vertically-oriented channel, dual-gate, CMOS FET John J. Seliskar, Verne Hornback 2002-03-12 $24,274,000
6316817 MeV implantation to form vertically modulated N+ buried layer in an NPN bipolar transistor John J. Seliskar, Todd A. Randazzo 2001-11-13 $23,602,000
6241847 Method and apparatus for detecting a polishing endpoint based upon infrared signals Derryl D. J. Allman, John Gregory 2001-06-05 $27,808,000
6235590 Fabrication of differential gate oxide thicknesses on a single integrated circuit chip Dianne G. Pinello, Michael F. Chisholm 2001-05-22 $33,865,000
6201253 Method and apparatus for detecting a planarized outer layer of a semiconductor wafer with a confocal optical system Derryl D. J. Allman, John Gregory 2001-03-13 $28,061,000
6121147 Apparatus and method of detecting a polishing endpoint layer of a semiconductor wafer which includes a metallic reporting substance John Gregory, Derryl D. J. Allman 2000-09-19 $25,929,000
6096625 Method for improved gate oxide integrity on bulk silicon Theodore Moore, Crystal J. Hass 2000-08-01 $23,151,000
6077783 Method and apparatus for detecting a polishing endpoint based upon heat conducted through a semiconductor wafer Derryl D. J. Allman, Michael F. Chisholm 2000-06-20 $83,568,000
6069048 Reduction of silicon defect induced failures as a result of implants in CMOS and other integrated circuits 2000-05-30 $26,487,000
5966599 Method for fabricating a low trigger voltage silicon controlled rectifier and thick field device John D. Walker 1999-10-12 $29,372,000
5858828 Use of MEV implantation to form vertically modulated N+ buried layer in an NPN bipolar transistor John J. Seliskar, Todd A. Randazzo 1999-01-12