Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Subtractive oxidation method of fabricating a short-length and vertically-oriented channel, dual-gate, CMOS FET

Subtractive oxidation method of fabricating a short-length and vertically-oriented channel, dual-gate, CMOS FET

US Patent 6355532 · Granted Mar 12, 2002

Estimated economic value: $24,274,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

System and method for identifying system vulnerabilities2021
Castellated gate MOSFET tetrode capable of fully-depleted operation2014
Application of gate edge liner to maintain gate length CD in a replacement gate 2013
Castellated gate MOSFET tetrode capable of fully-depleted operation2012
Mixed-signal semiconductor platform incorporating fully-depleted castellated-gat2011
Self-aligned cell integration scheme2011
Isolated metal plug process for use in fabricating carbon nanotube memory cells2011
Isolated metal plug process for use in fabricating carbon nanotube memory cells2010
Mixed-signal semiconductor platform incorporating fully-depleted castellated-gat2010
Castellated gate MOSFET device capable of fully-depleted operation2010
Fully-depleted castellated gate MOSFET device and method of manufacture thereof2008
Application of gate edge liner to maintain gate length CD in a replacement gate 2008