Issued Patents All Time
Showing 25 most recent of 46 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12429902 | Memory system, memory access interface device and operation method thereof | Fu-Chin Tsai, Ger-Chih Chou, Chih-Wei Chang, Min-Han Tsai | 2025-09-30 |
| 12417795 | Physical layer circuit, write leveling training circuit and method for calibrating access control signal transmitted to memory device | Fu-Chin Tsai, Chih-Wei Chang, Gerchih Chou | 2025-09-16 |
| 12300330 | Memory system and memory access interface device thereof for supporting different speed modes | Fu-Chin Tsai, Ger-Chih Chou, Chih-Wei Chang | 2025-05-13 |
| 12288583 | Memory controller and method for calibrating data reception window | Shih-Chang Chen, Chih-Wei Chang | 2025-04-29 |
| 12211699 | Method of removing step height on gate structure | Yeh-Sheng Lin, Chang-Mao Wang, Chung-Yi Chiu | 2025-01-28 |
| 12188982 | Test method for delay circuit and test circuitry | Kuo-Wei Chi, Chih-Wei Chang | 2025-01-07 |
| 12147163 | Method for correcting critical dimension measurements of lithographic tool | Hsin-Yu Hsieh, Kuan-Ying Lai, Chang-Mao Wang, Chien-Hao Chen | 2024-11-19 |
| 12106962 | Patterning method and overlay measurement method | Yi-Jing Wang, Chia-Chang Hsu, Chien-Hao Chen, Chang-Mao Wang | 2024-10-01 |
| 12088359 | Receiver of communication system and eye diagram measuring method | Shih-Chang Chen, Chih-Wei Chang | 2024-09-10 |
| 12009056 | Data transmission apparatus and method having clock gating mechanism | Fu-Chin Tsai, Ger-Chih Chou, Chih-Wei Chang, Shih-Han Lin | 2024-06-11 |
| 11978497 | DDR SDRAM signal calibration device and method | Kuo-Wei Chi, Chih-Wei Chang, Ger-Chih Chou | 2024-05-07 |
| 11823770 | Memory system and memory access interface device thereof | Ger-Chih Chou, Chih-Wei Chang, Li-Jun Gu, Fu-Chin Tsai | 2023-11-21 |
| 11816352 | Electronic device, data strobe gate signal generator circuit and data strobe gate signal generating method | Chih-Wei Chang, Gerchih Chou | 2023-11-14 |
| 11315656 | Detection circuit and detection method | Shih-Han Lin, Chih-Wei Chang, Gerchih Chou, Shih-Chang Chen, Kuo-Wei Chi +2 more | 2022-04-26 |
| 11270745 | Method of foreground auto-calibrating data reception window and related device | Shih-Chang Chen, Chih-Wei Chang, Kuo-Wei Chi, Fu-Chin Tsai, Shih-Han Lin +1 more | 2022-03-08 |
| 11043460 | Measurement method of overlay mark structure | Yu-Wei Cheng, Bo-Jou Lu | 2021-06-22 |
| 10998020 | Memory system and memory access interface device thereof | Fu-Chin Tsai, Chih-Wei Chang, Gerchih Chou, Kuo-Wei Chi, Shih-Chang Chen +2 more | 2021-05-04 |
| 10998061 | Memory system and memory access interface device thereof | Fu-Chin Tsai, Chih-Wei Chang, Gerchih Chou | 2021-05-04 |
| 10978118 | DDR SDRAM signal calibration device and method | Fu-Chin Tsai, Chih-Wei Chang, Gerchih Chou | 2021-04-13 |
| 10916278 | Memory controller and memory data receiving method for generate better sampling clock signal | Kuo-Wei Chi, Chih-Wei Chang, Gerchih Chou, Shih-Chang Chen, Fu-Chin Tsai +2 more | 2021-02-09 |
| 10916636 | Method of forming gate | Po-Tsang Chen, Wen-Liang Huang | 2021-02-09 |
| 10811362 | Overlay mark structure and measurement method thereof | Yu-Wei Cheng, Bo-Jou Lu | 2020-10-20 |
| 10741231 | Memory access interface device including phase and duty cycle adjusting circuits for memory access signals | Fu-Chin Tsai, Chih-Wei Chang, Gerchih Chou | 2020-08-11 |
| 10698846 | DDR SDRAM physical layer interface circuit and DDR SDRAM control device | Kuo-Wei Chi, Chih-Wei Chang, Gerchih Chou, Shih-Chang Chen | 2020-06-30 |
| 10643685 | Control circuit, sampling circuit for synchronous dynamic random-access memory, method of reading procedure and calibration thereof | Gerchih Chou, Chih-Wei Chang, Shen-Kuo Huang | 2020-05-05 |