Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12429902 | Memory system, memory access interface device and operation method thereof | Ger-Chih Chou, Chun-Chi Yu, Chih-Wei Chang, Min-Han Tsai | 2025-09-30 |
| 12417795 | Physical layer circuit, write leveling training circuit and method for calibrating access control signal transmitted to memory device | Chun-Chi Yu, Chih-Wei Chang, Gerchih Chou | 2025-09-16 |
| 12300330 | Memory system and memory access interface device thereof for supporting different speed modes | Ger-Chih Chou, Chun-Chi Yu, Chih-Wei Chang | 2025-05-13 |
| 12020773 | Memory system and memory access interface device thereof including single data rate (SDR) and double data rate (DDR) modes | — | 2024-06-25 |
| 12009056 | Data transmission apparatus and method having clock gating mechanism | Ger-Chih Chou, Chun-Chi Yu, Chih-Wei Chang, Shih-Han Lin | 2024-06-11 |
| 11823770 | Memory system and memory access interface device thereof | Ger-Chih Chou, Chih-Wei Chang, Li-Jun Gu, Chun-Chi Yu | 2023-11-21 |
| 11315656 | Detection circuit and detection method | Shih-Han Lin, Chun-Chi Yu, Chih-Wei Chang, Gerchih Chou, Shih-Chang Chen +2 more | 2022-04-26 |
| 11270745 | Method of foreground auto-calibrating data reception window and related device | Shih-Chang Chen, Chun-Chi Yu, Chih-Wei Chang, Kuo-Wei Chi, Shih-Han Lin +1 more | 2022-03-08 |
| 10998020 | Memory system and memory access interface device thereof | Chun-Chi Yu, Chih-Wei Chang, Gerchih Chou, Kuo-Wei Chi, Shih-Chang Chen +2 more | 2021-05-04 |
| 10998061 | Memory system and memory access interface device thereof | Chun-Chi Yu, Chih-Wei Chang, Gerchih Chou | 2021-05-04 |
| 10978118 | DDR SDRAM signal calibration device and method | Chun-Chi Yu, Chih-Wei Chang, Gerchih Chou | 2021-04-13 |
| 10916278 | Memory controller and memory data receiving method for generate better sampling clock signal | Kuo-Wei Chi, Chun-Chi Yu, Chih-Wei Chang, Gerchih Chou, Shih-Chang Chen +2 more | 2021-02-09 |
| 10741231 | Memory access interface device including phase and duty cycle adjusting circuits for memory access signals | Chun-Chi Yu, Chih-Wei Chang, Gerchih Chou | 2020-08-11 |
| 10522204 | Memory signal phase difference calibration circuit and method | Chun-Chi Yu, Shih-Han Lin, Chih-Wei Chang, Gerchih Chou | 2019-12-31 |
| 9570130 | Memory system and memory physical layer interface circuit | Chun-Chi Yu, Chih-Wei Chang, Gerchih Chou, Shih-Chang Chen | 2017-02-14 |