Issued Patents All Time
Showing 25 most recent of 50 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12417795 | Physical layer circuit, write leveling training circuit and method for calibrating access control signal transmitted to memory device | Fu-Chin Tsai, Chun-Chi Yu, Chih-Wei Chang | 2025-09-16 |
| 11816352 | Electronic device, data strobe gate signal generator circuit and data strobe gate signal generating method | Chun-Chi Yu, Chih-Wei Chang | 2023-11-14 |
| 11315656 | Detection circuit and detection method | Shih-Han Lin, Chun-Chi Yu, Chih-Wei Chang, Shih-Chang Chen, Kuo-Wei Chi +2 more | 2022-04-26 |
| 11270745 | Method of foreground auto-calibrating data reception window and related device | Shih-Chang Chen, Chun-Chi Yu, Chih-Wei Chang, Kuo-Wei Chi, Fu-Chin Tsai +1 more | 2022-03-08 |
| 11251801 | Frequency adjusting apparatus and frequency adjusting method | Chih-Hsiung Hsu, Han-Chieh Hsieh | 2022-02-15 |
| 10998020 | Memory system and memory access interface device thereof | Fu-Chin Tsai, Chun-Chi Yu, Chih-Wei Chang, Kuo-Wei Chi, Shih-Chang Chen +2 more | 2021-05-04 |
| 10998061 | Memory system and memory access interface device thereof | Fu-Chin Tsai, Chun-Chi Yu, Chih-Wei Chang | 2021-05-04 |
| 10978118 | DDR SDRAM signal calibration device and method | Chun-Chi Yu, Fu-Chin Tsai, Chih-Wei Chang | 2021-04-13 |
| 10916278 | Memory controller and memory data receiving method for generate better sampling clock signal | Kuo-Wei Chi, Chun-Chi Yu, Chih-Wei Chang, Shih-Chang Chen, Fu-Chin Tsai +2 more | 2021-02-09 |
| 10741231 | Memory access interface device including phase and duty cycle adjusting circuits for memory access signals | Fu-Chin Tsai, Chun-Chi Yu, Chih-Wei Chang | 2020-08-11 |
| 10698846 | DDR SDRAM physical layer interface circuit and DDR SDRAM control device | Kuo-Wei Chi, Chun-Chi Yu, Chih-Wei Chang, Shih-Chang Chen | 2020-06-30 |
| 10643685 | Control circuit, sampling circuit for synchronous dynamic random-access memory, method of reading procedure and calibration thereof | Chun-Chi Yu, Chih-Wei Chang, Shen-Kuo Huang | 2020-05-05 |
| 10630289 | On-die-termination circuit and control method for of the same | Shen-Kuo Huang, Chun-Chi Yu, Chih-Wei Chang | 2020-04-21 |
| 10522204 | Memory signal phase difference calibration circuit and method | Chun-Chi Yu, Fu-Chin Tsai, Shih-Han Lin, Chih-Wei Chang | 2019-12-31 |
| 10382232 | Memory controller with adjustable impedance for output terminal | Shih-Hung Wang, Shen-Kuo Huang, Wen-Shan Wang | 2019-08-13 |
| 10347325 | DDR4 memory I/O driver | Li-Jun Gu | 2019-07-09 |
| 10056124 | Memory control device for repeating data during a preamble signal or a postamble signal and memory control method | Chun-Chi Yu, Chih-Wei Chang, Shen-Kuo Huang | 2018-08-21 |
| 9948280 | Two-capacitor-based filter design method and two-capacitor-based filter | Po-Chun Chen, Ruey-Beei Wu, Ting-Ying Wu, Wen-Shan Wang | 2018-04-17 |
| 9570130 | Memory system and memory physical layer interface circuit | Chun-Chi Yu, Chih-Wei Chang, Fu-Chin Tsai, Shih-Chang Chen | 2017-02-14 |
| 9350529 | Method and apparatus for detecting logical signal | Chia-Liang Lin | 2016-05-24 |
| 8665921 | Method and apparatus of automatic power control for burst mode laser transmitter | Chi-Kung Kuan, Chia-Liang Lin | 2014-03-04 |
| 8648640 | Method and apparatus for clock transmission | Chia-Liang Lin | 2014-02-11 |
| 8410834 | All digital serial link receiver with low jitter clock regeneration and method thereof | Chia-Liang Lin, Pei-Si Wu | 2013-04-02 |
| 8363774 | Methods and apparatuses of serial link transceiver without external reference clock | Chia-Liang Lin, Hong-Yean Hsieh | 2013-01-29 |
| 8324982 | Integrated front-end passive equalizer and method thereof | Chia-Liang Lin | 2012-12-04 |