| 6633971 |
Mechanism for forward data in a processor pipeline using a single pipefile connected to the pipeline |
Lew G. Chua-Eoan |
2003-10-14 |
| 6542983 |
Microcomputer/floating point processor interface and method |
Margaret Rose Gearty |
2003-04-01 |
| 6477638 |
Synchronized instruction advancement through CPU and FPU pipelines |
Margaret Rose Gearty |
2002-11-05 |
| 6457118 |
Method and system for selecting and using source operands in computer system instructions |
Glenn Ashley Farrall, Sivaram Krishnan |
2002-09-24 |
| 6449712 |
Emulating execution of smaller fixed-length branch/delay slot instructions with a sequence of larger fixed-length instructions |
Naohiko Irie, Tony L. Werner, Sebastian Haviuj Ziesler, Jackie Andrew Freeman, Sivaram Krishnan |
2002-09-10 |
| 6408381 |
Mechanism for fast access to control space in a pipeline processor |
Margaret Rose Gearty |
2002-06-18 |
| 6393523 |
Mechanism for invalidating instruction cache blocks in a pipeline processor |
Margaret Rose Gearty, Naohiko Irie, Tony L. Werner |
2002-05-21 |
| 6351803 |
Mechanism for power efficient processing in a pipeline processor |
Lew G. Chua-Eoan |
2002-02-26 |
| 5974535 |
Method and system in data processing system of permitting concurrent processing of instructions of a particular type |
Daniel C. Chow, Terence M. Potter, Paul C. Rossbach |
1999-10-26 |
| 5682495 |
Fully associative address translation buffer having separate segment and page invalidation |
Brad B. Beavers, Lew G. Chua-Eoan, Pei-Chun Liu |
1997-10-28 |
| 5604879 |
Single array address translator with segment and page invalidate ability and method of operation |
Brad B. Beavers, Chua-Eoan Lew, Pei-Chun Liu |
1997-02-18 |
| 5535351 |
Address translator with by-pass circuit and method of operation |
— |
1996-07-09 |
| 5530822 |
Address translator and method of operation |
Brad B. Beavers, Lew G. Chua-Eoan |
1996-06-25 |
