Issued Patents All Time
Showing 25 most recent of 72 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12417195 | Techniques for command bus training to a memory device | Steven T. TAYLOR, Alvin Shing Chye Goh | 2025-09-16 |
| 12355445 | Techniques for duty cycle correction | Ralph S. Li, Chin Wah Lim, Mahmoud Elassal, Anant Balakrishnan, Isaac Ali | 2025-07-08 |
| 12321214 | Fast self-refresh exit power state | Robert J. Royer, Jr., Aaron Martin, Alex Thomas, Tomer Levy, Noam Lupovich | 2025-06-03 |
| 12230569 | Apparatus and method to increase effective capacitance with layout staples | Kushal Sreedhar, Mahmoud Elassal | 2025-02-18 |
| 12093195 | Techniques for command bus training to a memory device | Steven T. TAYLOR, Alvin Shing Chye Goh | 2024-09-17 |
| 11916554 | Techniques for duty cycle correction | Ralph S. Li, Chin Wah Lim, Mahmoud Elassal, Anant Balakrishnan, Isaac Ali | 2024-02-27 |
| 11675716 | Techniques for command bus training to a memory device | Steven T. TAYLOR, Alvin Shing Chye Goh | 2023-06-13 |
| 11675532 | Memory command that specifies one of multiple possible write data values where the write data is not transported over a memory data bus | Christopher E. Cox | 2023-06-13 |
| 11335395 | Applying chip select for memory device identification and power management control | Christopher E. Cox, Kuljit S. Bains, James A. McCall, Akshith Vasanth, Bill Nale | 2022-05-17 |
| 11226762 | Memory command that specifies one of multiple possible write data values where the write data is not transported over a memory data bus | Christopher E. Cox | 2022-01-18 |
| 11159154 | Power gate ramp-up control apparatus and method | Eliyah Kilada | 2021-10-26 |
| 11074959 | DDR memory bus with a reduced data strobe signal preamble timespan | James A. McCall, Christopher E. Cox, Yan Fu, Robert J. Friar, Hsien-Pao Yang | 2021-07-27 |
| 11061590 | Efficiently training memory device chip select control | Tonia G. Morris, Christopher E. Cox | 2021-07-13 |
| 11037607 | Strong arm latch with wide common mode range | Raymond Chong, Bee Min Teng | 2021-06-15 |
| 10923164 | Dual power I/O transmitter | Hariprasath Venkatram, Mohammed G. Mostofa, Rajesh INTI, Roger K. Cheng, Aaron Martin +5 more | 2021-02-16 |
| 10839887 | Applying chip select for memory device identification and power management control | Christopher E. Cox, Kuljit S. Bains, James A. McCall, Akshith Vasanth, Bill Nale | 2020-11-17 |
| 10802996 | Dynamic bus inversion with programmable termination level to maintain programmable target ratio of ones and zeros in signal lines | James A. McCall, Bryan K. Casper | 2020-10-13 |
| 10672438 | Dynamic reconfigurable dual power I/O receiver | Mohammed G. Mostofa, Roger K. Cheng, Aaron Martin, Pavan Kumar Kappagantula, Hsien-Pao Yang | 2020-06-02 |
| 10573272 | Device, method and system for providing a delayed clock signal to a circuit for latching data | Senthil Kumar Sampath | 2020-02-25 |
| 10541018 | DDR memory bus with a reduced data strobe signal preamble timespan | James A. McCall, Christopher E. Cox, Yan Fu, Robert J. Friar, Hsien-Pao Yang | 2020-01-21 |
| 10516439 | Interference testing | Alexey Kostinsky, Tomer Levy, Paul S. Cheses, Danny Naiger, Theodore Z. Schoenborn +2 more | 2019-12-24 |
| 10446222 | Memory subsystem I/O performance based on in-system empirical testing | Theodore Z. Schoenborn | 2019-10-15 |
| 10437746 | Dynamic bus inversion with programmable termination level to maintain programmable target ratio of ones and zeros in signal lines | James A. McCall, Bryan K. Casper | 2019-10-08 |
| 10416912 | Efficiently training memory device chip select control | Tonia G. Morris, Christopher E. Cox | 2019-09-17 |
| 10373948 | On-die system electrostatic discharge protection | Victor Zia, Gabriel J. Thompson | 2019-08-06 |