Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10325054 | Invariant sharing to speed up formal verification | Himanshu Jain, Per M. Bjesse | 2019-06-18 |
| 9870442 | Equivalence checking between two or more circuit designs that include square root circuits | Himanshu Jain | 2018-01-16 |
| 9501597 | Elimination of illegal states within equivalence checking | Himanshu Jain | 2016-11-22 |
| 9189581 | Equivalence checking between two or more circuit designs that include division circuits | Himanshu Jain | 2015-11-17 |
| 8914758 | Equivalence checking using structural analysis on data flow graphs | Sudipta Kundu | 2014-12-16 |
| 8732637 | Formal verification of bit-serial division and bit-serial square-root circuit designs | Himanshu Jain | 2014-05-20 |
| 8589836 | Formally checking equivalence using equivalence relationships | Alfred Koelbl | 2013-11-19 |
| 8079000 | Method and apparatus for performing formal verification using data-flow graphs | Alfred Koelbl | 2011-12-13 |
| 8001500 | Method and apparatus for formally checking equivalence using equivalence relationships | Alfred Koelbl | 2011-08-16 |
| 7836414 | Formally proving the functional equivalence of pipelined designs containing memories | Alfred Koelbl, Jerry R. Burch | 2010-11-16 |
| 7523423 | Method and apparatus for production of data-flow-graphs by symbolic simulation | Alfred Koelbl | 2009-04-21 |
| 7509604 | Method and apparatus for formally comparing stream-based designs | Alfred Koelbl | 2009-03-24 |
| 7509599 | Method and apparatus for performing formal verification using data-flow graphs | Alfred Koelbl | 2009-03-24 |
| 7389479 | Formally proving the functional equivalence of pipelined designs containing memories | Alfred Koelbl, Jerry R. Burch | 2008-06-17 |
| 7386820 | Method and apparatus for formally checking equivalence using equivalence relationships | Alfred Koelbl | 2008-06-10 |
| 7260800 | Method and apparatus for initial state extraction | Alfred Koelbl | 2007-08-21 |
| 7107553 | Method and apparatus for solving constraints | Brian Lockyear, James H. Kukula, Robert F. Damiano | 2006-09-12 |
| 6321186 | Method and apparatus for integrated circuit design verification | Jun Yuan, Stephen Shultz, Hillel Miller | 2001-11-20 |
| 5999717 | Method for performing model checking in integrated circuit design | Matthew Kaufmann, Andrew K. Martin | 1999-12-07 |
| 5754454 | Method for determining functional equivalence between design models | Jaehong Park | 1998-05-19 |
| 5680332 | Measurement of digital circuit simulation test coverage utilizing BDDs and state bins | Richard Raimi | 1997-10-21 |
| 5638381 | Apparatus and method for deriving correspondence between storage elements of a first circuit model and storage elements of a second circuit model | Hyunwoo Cho | 1997-06-10 |
| 5572535 | Method and data processing system for verifying the correct operation of a tri-state multiplexer in a circuit design | Hyunwoo Cho, Bernard Plessier, Jesse R. Wilson, Ralph McGarity | 1996-11-05 |
| 5331568 | Apparatus and method for determining sequential hardware equivalence | — | 1994-07-19 |