Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10782896 | Local instruction ordering based on memory domains | Shubhendu Sekhar Mukherjee, Richard E. Kessler, Mike Bertone, Chris Comis | 2020-09-22 |
| 10394730 | Distributed interrupt scheme in a multi-processor system | Wu Ye, Yoganand Chillarige, Paul G. Scrobohaci, Scott Lurndal | 2019-08-27 |
| 10216430 | Local ordering of instructions in a computing system | Shubhendu Sekhar Mukherjee, Richard E. Kessler, Mike Bertone, Chris Comis | 2019-02-26 |
| 10042778 | Collapsed address translation with multiple page sizes | Shubhendu Sekhar Mukherjee, Wilson P. Snyder, II, Michael Bertone, Richard E. Kessler, Christopher Mikulis | 2018-08-07 |
| 10007614 | Method and apparatus for determining metric for selective caching | Xiaodong Wang, Srilatha Manne, Isam Akkawi, David Asher | 2018-06-26 |
| 9928193 | Distributed timer subsystem | Frank Worrell | 2018-03-27 |
| 9703669 | Apparatus and method for distributed instruction trace in a processor system | Gerald Lampert, David William Kravitz | 2017-07-11 |
| 9645941 | Collapsed address translation with multiple page sizes | Shubhendu Sekhar Mukherjee, Wilson P. Snyder, II, Michael Bertone, Richard E. Kessler, Christopher Mikulis | 2017-05-09 |
| 9639476 | Merged TLB structure for multiple sequential address translations | Shubhendu Sekhar Mukherjee, Wilson P. Snyder, II, Michael Bertone, Richard E. Kessler | 2017-05-02 |
| 9568944 | Distributed timer subsystem across multiple devices | Frank Worrell | 2017-02-14 |
| 9495161 | QoS based dynamic execution engine selection | Najeeb I. Ansari, Michael Carns, Jeffrey Schroeder | 2016-11-15 |
| 9404970 | Debug interface for multiple CPU cores | Teng Chiang Lin, Gerald Lampert, Nitin Prakash, Andy Wang | 2016-08-02 |
| 9372800 | Inter-chip interconnect protocol for a multi-chip system | Isam Akkawi, Richard E. Kessler, David Asher, Wilson P. Snyder, II | 2016-06-21 |
| 9268694 | Maintenance of cache and tags in a translation lookaside buffer | Wilson P. Snyder, II, Shubhendu Sekhar Mukherjee, Michael Bertone, Richard E. Kessler | 2016-02-23 |
| 9208103 | Translation bypass in multi-stage address translation | Richard E. Kessler, Michael Bertone | 2015-12-08 |
| 9128769 | Processor with dedicated virtual functions and dynamic assignment of functional resources | Jeffrey Schroeder, Jeff Pangborn, Najeeb I. Ansari, Leo Chen, Ahmed Shahid +5 more | 2015-09-08 |
| 9129060 | QoS based dynamic execution engine selection | Najeeb I. Ansari, Michael Carns, Jeffrey Schroeder | 2015-09-08 |
| 8989220 | High speed variable bandwidth ring-based system | Paul G. Scrobohaci, Ahmed Shahid, Leo Chen | 2015-03-24 |
| 7613882 | Fast invalidation for cache coherency in distributed shared memory system | Isam Akkawi, Michael S. Woodacre, Krishnan Subramani, Najeeb I. Ansari, Chetana N. Keltcher +1 more | 2009-11-03 |