Issued Patents All Time
Showing 25 most recent of 30 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11729640 | Methods and apparatus for configuring a front end to process multiple sectors with multiple radio frequency frames | Mehran Nekuii, Hong Jik Kim | 2023-08-15 |
| 11172379 | Methods and apparatus for configuring a front end to process multiple sectors with multiple radio frequency frames | Mehran Nekuii, Hong Jik Kim | 2021-11-09 |
| 9928193 | Distributed timer subsystem | Bryan W. Chin | 2018-03-27 |
| 9667446 | Condition code approach for comparing rule and packet data that are provided in portions | — | 2017-05-30 |
| 9568944 | Distributed timer subsystem across multiple devices | Bryan W. Chin | 2017-02-14 |
| 9544402 | Multi-rule approach to encoding a group of rules | Rajan Goyal, Satyanarayana Lakshmipathi Billa | 2017-01-10 |
| 8046505 | Systems for implementing SDRAM controllers, and buses adapted to include advanced high performance bus features | Keith D. Au | 2011-10-25 |
| 7966431 | Systems for implementing SDRAM controllers, and buses adapted to include advanced high performance bus features | Keith D. Au | 2011-06-21 |
| 7797467 | Systems for implementing SDRAM controllers, and buses adapted to include advanced high performance bus features | Keith D. Au | 2010-09-14 |
| 7681017 | Pseudo pipeline and pseudo pipelined SDRAM controller | — | 2010-03-16 |
| 7069363 | On-chip bus | — | 2006-06-27 |
| 6973561 | Processor pipeline stall based on data register status | Rene Vangemert, Gagan V. Gupta | 2005-12-06 |
| 6948054 | Simple branch prediction and misprediction recovery method | — | 2005-09-20 |
| 6877082 | Central processing unit including address generation system and instruction fetch apparatus | — | 2005-04-05 |
| 6728816 | Simple mechanism for guaranteeing in order read data return on a split transaction bus | — | 2004-04-27 |
| 6671781 | Data cache store buffer | — | 2003-12-30 |
| 6584537 | Data-cache data-path | Gagan V. Gupta | 2003-06-24 |
| 6412066 | Microprocessor employing branch instruction to set compression mode | Hartvig Ekner | 2002-06-25 |
| 6012138 | Dynamically variable length CPU pipeline for efficiently executing two instruction sets | — | 2000-01-04 |
| 5982194 | Arithmetic and logic function circuits optimized for datapath layout | — | 1999-11-09 |
| 5931941 | Interface for a modularized computational unit to a CPU | — | 1999-08-03 |
| 5905893 | Microprocessor adapted for executing both a non-compressed fixed length instruction set and a compressed variable length instruction set | — | 1999-05-18 |
| 5896519 | Apparatus for detecting instructions from a variable-length compressed instruction set having extended and non-extended instructions | — | 1999-04-20 |
| 5867681 | Microprocessor having register dependent immediate decompression | Hartvig Ekner | 1999-02-02 |
| 5794010 | Method and apparatus for allowing execution of both compressed instructions and decompressed instructions in a microprocessor | Hartvig Ekner | 1998-08-11 |