AC

Arvind Chokhani

CS Cadence Design Systems: 7 patents #204 of 2,263Top 10%
Overall (All Time): #690,765 of 4,157,543Top 20%
7
Patents All Time

Issued Patents All Time

Showing 1–7 of 7 patents

Patent #TitleCo-InventorsDate
11892501 Diagnosing multicycle transition faults and/or defects with AT-speed ATPG test patterns Joseph Michael Swenton, Martin Thomas Amodeo 2024-02-06
11893336 Utilizing transition ATPG test patterns to detect multicycle faults and/or defects in an IC chip Joseph Michael Swenton, Martin Thomas Amodeo 2024-02-06
11740284 Diagnosing multicycle faults and/or defects with single cycle ATPG test patterns Joseph Michael Swenton, Martin Thomas Amodeo 2023-08-29
11579194 Utilizing single cycle ATPG test patterns to detect multicycle cell-aware defects Joseph Michael Swenton, Martin Thomas Amodeo 2023-02-14
11461520 SDD ATPG using fault rules files, SDF and node slack for testing an IC chip Joseph M. Swenton, Santosh Subhaschandra Malagi 2022-10-04
11435401 Timed transition cell-aware ATPG using fault rule files and SDF for testing an IC chip Joseph Michael Swenton, Santosh Subhaschandra Malagi 2022-09-06
11429776 Fault rules files for testing an IC chip Joseph Michael Swenton, Santosh Subhaschandra Malagi 2022-08-30