SM

Santosh Subhaschandra Malagi

CS Cadence Design Systems: 3 patents #541 of 2,263Top 25%
📍 Endicott, NY: #211 of 620 inventorsTop 35%
🗺 New York: #38,318 of 115,490 inventorsTop 35%
Overall (All Time): #1,419,935 of 4,157,543Top 35%
3
Patents All Time

Issued Patents All Time

Showing 1–3 of 3 patents

Patent #TitleCo-InventorsDate
11461520 SDD ATPG using fault rules files, SDF and node slack for testing an IC chip Arvind Chokhani, Joseph M. Swenton 2022-10-04
11435401 Timed transition cell-aware ATPG using fault rule files and SDF for testing an IC chip Arvind Chokhani, Joseph Michael Swenton 2022-09-06
11429776 Fault rules files for testing an IC chip Arvind Chokhani, Joseph Michael Swenton 2022-08-30