Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7719295 | Method and apparatus for implementing IC device testing with improved SPQL, reliability and yield performance | — | 2010-05-18 |
| 6332988 | Rework process | Russell G. Berger, Jr. | 2001-12-25 |
| 6114181 | Pre burn-in thermal bump card attach simulation to enhance reliability | — | 2000-09-05 |
| 5804459 | Method for charge enhanced defect breakdown to improve yield and reliability | Ronald J. Bolam | 1998-09-08 |
| 5576246 | Personalized area leadframe coining or half etching for reduced mechanical stress at device edge | Harold W. Conru, Francis E. Froebel, Sheldon C. Rieley, Stephen G. Starr, Ronald R. Uttecht +2 more | 1996-11-19 |
| 5545921 | Personalized area leadframe coining or half etching for reduced mechanical stress at device edge | Harold W. Conru, Francis E. Froebel, Sheldon C. Rieley, Stephen G. Starr, Ronald R. Uttecht +2 more | 1996-08-13 |