Issued Patents All Time
Showing 101–125 of 241 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5793247 | Constant current source with reduced sensitivity to supply voltage and process variation | — | 1998-08-11 |
| 5790462 | Redundancy control | — | 1998-08-04 |
| 5771195 | Circuit and method for replacing a defective memory cell with a redundant memory cell | — | 1998-06-23 |
| 5767709 | Synchronous test mode initalization | — | 1998-06-16 |
| 5768206 | Circuit and method for biasing bit lines | — | 1998-06-16 |
| 5764592 | External write pulse control method and structure | — | 1998-06-09 |
| 5745420 | Integrated memory circuit with sequenced bitlines for stress test | — | 1998-04-28 |
| 5745432 | Write driver having a test function | — | 1998-04-28 |
| 5719445 | Input delay control | — | 1998-02-17 |
| 5712584 | Synchronous stress test control | — | 1998-01-27 |
| 5708789 | Structure to utilize a partially functional cache memory by invalidation of faulty cache memory locations | — | 1998-01-13 |
| 5706232 | Semiconductor memory with multiple clocking for test mode entry | Thomas A. Coker | 1998-01-06 |
| 5703512 | Method and apparatus for test mode entry during power up | — | 1997-12-30 |
| 5701275 | Pipelined chip enable control circuitry and methodology | — | 1997-12-23 |
| 5691950 | Device and method for isolating bit lines from a data line | — | 1997-11-25 |
| 5666482 | Method and system for bypassing a faulty line of data or its associated tag of a set associative cache memory | — | 1997-09-09 |
| 5657292 | Write pass through circuit | — | 1997-08-12 |
| 5654663 | Circuit for providing a compensated bias voltage | Thomas A. Teel | 1997-08-05 |
| 5644542 | Stress test for memory arrays in integrated circuits | James Brady | 1997-07-01 |
| 5640122 | Circuit for providing a bias voltage compensated for p-channel transistor variations | — | 1997-06-17 |
| 5633828 | Circuitry and methodology to test single bit failures of integrated circuit memory devices | Mark A. Lysinger, Frank J. Sigmund, John A. Michlowsky | 1997-05-27 |
| 5629896 | Write controlled address buffer | — | 1997-05-13 |
| 5629943 | Integrated circuit memory with double bitline low special test mode control from output enable | — | 1997-05-13 |
| 5627787 | Periphery stress test for synchronous RAMs | — | 1997-05-06 |
| 5627793 | Clock generation circuit having compensation for semiconductor manufacturing process variations | — | 1997-05-06 |