Issued Patents All Time
Showing 151–175 of 241 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5568084 | Circuit for providing a compensated bias voltage | Thomas A. Teel | 1996-10-22 |
| 5557573 | Entire wafer stress test method for integrated memory devices and circuit therefor | — | 1996-09-17 |
| 5551004 | Structure which renders faulty data of a cache memory uncacheable in order that a partially functional cache memory may be utilized | — | 1996-08-27 |
| 5548241 | Voltage reference circuit using an offset compensating current source | — | 1996-08-20 |
| 5546537 | Method and apparatus for parallel testing of memory | — | 1996-08-13 |
| 5544097 | SRAM memory cell with reduced internal cell voltage | Mehdi Zamanian | 1996-08-06 |
| 5530674 | Structure capable of simultaneously testing redundant and non-redundant memory elements during stress testing of an integrated circuit memory device | Thomas A. Teel | 1996-06-25 |
| 5526318 | Semiconductor memory with power-on reset controlled latched row line repeaters | William C. Slemmer | 1996-06-11 |
| 5526317 | Structure for using a portion of an integrated circuit die | — | 1996-06-11 |
| 5521880 | Integrated circuit memory having control circuitry for shared data bus | — | 1996-05-28 |
| 5517455 | Integrated circuit with fuse circuitry simulating fuse blowing | William C. Slemmer | 1996-05-14 |
| 5513335 | Cache tag memory having first and second single-port arrays and a dual-port array | — | 1996-04-30 |
| 5513143 | Data cache memory internal circuitry for reducing wait states | — | 1996-04-30 |
| 5508679 | FIFO with adaptable flags for changing system speed requirements | — | 1996-04-16 |
| 5502655 | Difference comparison between two asynchronous pointers and a programmable value | — | 1996-03-26 |
| 5502678 | Full memory chip long write test mode | — | 1996-03-26 |
| 5495446 | Pre-charged exclusionary wired-connected programmed redundant select | Thomas A. Teel | 1996-02-27 |
| 5493532 | Integrated circuit memory with disabled edge transition pulse generation during special test mode | — | 1996-02-20 |
| 5493537 | Semiconductor memory with edge transition detection pulse disable | — | 1996-02-20 |
| 5491444 | Fuse circuit with feedback disconnect | — | 1996-02-13 |
| 5487048 | Multiplexing sense amplifier | — | 1996-01-23 |
| 5485430 | Multiple clocked dynamic sense amplifier | — | 1996-01-16 |
| 5483489 | Multiplexing sense amplifier | — | 1996-01-09 |
| 5473567 | Disabling sense amplifier | — | 1995-12-05 |
| 5471431 | Structure to recover a portion of a partially functional embedded memory | — | 1995-11-28 |