Issued Patents All Time
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7688669 | Programmable SRAM source bias scheme for use with switchable SRAM power supply sets of voltages | David C. McClure, Mark A. Lysinger, Francois Jacquet, Philippe Roche | 2010-03-30 |
| 7064534 | Regulator circuitry and method | David C. McClure | 2006-06-20 |
| 6903616 | Startup circuit and method for starting an oscillator after power-off | Rong Yin | 2005-06-07 |
| 6759717 | CMOS integrated circuit device with LDD n-channel transistor and non-LDD p-channel transistor | Pervez Hassan Sagarwala, Ravi Sundaresan | 2004-07-06 |
| 6486649 | Built-in frequency test circuit for testing the frequency of the output of a frequency generating circuit | Rong Yin | 2002-11-26 |
| 6486007 | Method of fabricating a memory cell for a static random access memory | Tsiu C. Chan, David C. McClure | 2002-11-26 |
| 6295224 | Circuit and method of fabricating a memory cell for a static random access memory | Tsiu C. Chan, David C. McClure | 2001-09-25 |
| 6221709 | Method of fabricating a CMOS integrated circuit device with LDD N-channel transistor and non-LDD P-channel transistor | Pervez Hassan Sagarwala, Ravi Sundaresan | 2001-04-24 |
| 6194276 | Radiation hardened semiconductor memory | Tsiu C. Chan | 2001-02-27 |
| 6180517 | Method of forming submicron contacts and vias in an integrated circuit | Fu-Tai Liou | 2001-01-30 |
| 6153458 | Method of forming a portion of a memory cell | James L. Worley | 2000-11-28 |
| 6111319 | Method of forming submicron contacts and vias in an integrated circuit | Fu-Tai Liou | 2000-08-29 |
| 6091630 | Radiation hardened semiconductor memory | Tsiu C. Chan | 2000-07-18 |
| 6057699 | Built-in frequency test circuit for testing the frequency of the output of a frequency generating circuit | Rong Yin | 2000-05-02 |
| 6033980 | Method of forming submicron contacts and vias in an integrated circuit | Fu-Tai Liou | 2000-03-07 |
| 5847460 | Submicron contacts and vias in an integrated circuit | Fu-Tai Liou | 1998-12-08 |
| 5793111 | Barrier and landing pad structure in an integrated circuit | — | 1998-08-11 |
| 5633196 | Method of forming a barrier and landing pad structure in an integrated circuit | — | 1997-05-27 |
| 5544097 | SRAM memory cell with reduced internal cell voltage | David C. McClure | 1996-08-06 |
| 5521401 | P-N junction in a vertical memory cell that creates a high resistance load | James L. Worley | 1996-05-28 |
| 5272371 | Electrostatic discharge protection structure | William A. Bishop, Tsiu C. Chan | 1993-12-21 |
| 5171700 | Field effect transistor structure and method | — | 1992-12-15 |
| 5116777 | Method for fabricating semiconductor devices by use of an N.sup.+ buried layer for complete isolation | Tsiu C. Chan | 1992-05-26 |